Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit

Arithmetic Logic Unit (ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4 (Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.

Reversible circuits have widespread applications in quantum computing, low power circuit design, nanotechnology, cryptography etc. The paper addresses the fault diagnosis problem in reversible logic circuit for missing gate fault model. The key idea of this paper is to extract the fault signature for each of the missing gate faults in a reversible circuit. Fault signatures are generated using the successive tree form of Multi-Input Signature Analyzer (MISA). Fault diagnosis is performed by verifying the signature of the circuit under test. The proposed method rapidly identifies the fault locations and the experimental results for benchmark circuits exhibit the efficiency of the technique.

Design of integrated reversible fault-tolerant arithmetic and logic unit

Reversible logic has received a great deal of attention from many researchers over recent years for its enormous potential for application in quantum computing and nanotechnology due to its ability to reduce power consumption, which is the main requirement in low power VLSI design. In this study, first, we have presented new reversible blocks. These circuits can be used for the design of a large and complex combinational circuit. Then, we presented optimised designs for the various reversible components: multiplexers, registers, and shift registers. We will put forward the design and evaluation of optimised reversible division hardware to submit an application of reversible logic design. The comparative results show that the proposed designs individually have less hardware complexity, garbage outputs, constant inputs, quantum cost and significantly better scalability than the existing works. We have presented some lower bounds on the cost-metrics for designing the reversible components of the divider circuit.

Reversible logic has extensive applications in quantum computing, low power VLSI design, quantum dot cellular automata and optical computing. While several researchers have investigated the design of reversible logic elements, there is not much work reported on reversible binary subtractors. In this paper, we propose the design of a new reversible gate called TR gate. Further, we investigate the design of reversible binary subtractors based on the proposed TR gate. The proposed TR gate is better for designing reversible binary subtractor compared to such gates discussed in literature in terms of quantum cost, garbage outputs and complexity of gates.

An improved KFDD based reversible circuit synthesis method

In today’s electrical or electronic designing, power dissipation becomes dominant. The promising alternative to these technologies is the reversible computing. Because for irreversible circuits, information is lost and it dissipates energy as heat. The dissipated energy is proportional to the number of bits lost during computation. In case of reversible circuits, they do not dissipate energy in a large amount as irreversible circuits. So information is not lost in reversible circuits during the execution of operation. Thus generation of unique outputs from the particular inputs and reconstruction of inputs from the particular outputs can be achievable. So in the view point of designing issues, reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing and other emerging computing technologies, bioinformatics and nanotechnology-based systems. Here, an approach for the designing of optimized reversible parallel multiplier (ORPM) by reversible gates has been followed. In this regard, this paper represents a new partial reversible gate RPPG for partial product generation for the designing of ORPM. Also, two designing methods are proposed to design ORPM and a comparison is also made between these two methods and the existing reversible multiplier circuits reported in the literature in perspective of the number of reversible gates, constant input, garbage output and total logical calculation.KeywordsReversible logicReversible gateReversible parallel multiplierGarbage outputConstant inputs

Over the last few decades, research in reversible logic has increasingly become very popular and it is gaining greater momentum in the present word. Reversible logic has started finding concert applications in quantum computing, optical computing, nano-technology based system, low-power CMOS design, VLSI design. The principal objective of this work is to argue for quantum implementation of various reversible logic gates by using C-NOT, Controlled-V and Controlled-V+ gates. The present work presents Binary coded decimal adder (BCD) in terms of number of gates, garbage outputs, quantum cost, delay and hardware complexity compared to existing design.

Reversible circuit synthesis is an important field in quantum computing, low-power design, and reversible circuit. The problem of reversible circuit synthesis is complicated and hard to solve because the input of the reversible circuit will experience a huge increase when extended to multi-bit. In this paper, a novel algorithm of reversible circuit synthesis is proposed. With the satisfied priority of positions, we can efficiently select the position which should be satisfied, and each selected gate is generated to benefit the overall situation. Therefore, the proposed algorithm is able to optimize the reversible circuit with fewer gates and can be implemented in regard to multibit reversible circuit synthesis. In addition, the gate set we used contains only Toffoli, spanning all wires. This Toffoli gate is liable to be transformed into another gate set and is helpful for algorithm design. The experiment shows that the proposed algorithm, with efficient and optimal results, is superior to others.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

The design of reversible logic circuits has received considerable attention in recent times for their potential use in implementing quantum computers. A fault model, namely, the Missing-Gate Fault (MGF) model, has been found to be more suitable for modeling defects in quantum circuits as compared to the classical fault models used for testing conventional CMOS circuits. In this paper, we propose two design-for-testability techniques with universal test set to detect MGFs in a reversible circuit. In these techniques, an [Formula: see text] reversible circuit implemented with [Formula: see text]-CNOT gates is transformed to a testable design with addition of two extra inputs lines and some additional gates, which uses a universal test set of size [Formula: see text] to detect the MGFs. The proposed DFT techniques are compared with earlier works and it has been shown that these techniques outperform the earlier techniques with respect to quantum cost overhead and percentage detection of the different MGFs.

Fault-tolerant quantum reversible full adder/subtractor: Design and implementation

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. In this paper, we propose an improved technique for synthesizing reversible circuits based on a combined depth-first search (DFS) and breadth-first search (BFS) algorithm. A method based on DFS alone may often take a long time to converge, whereas, a BFS based method requires a large amount of memory for designing a circuit of moderate complexity. To strike a balance between these two approaches, we propose a hybrid DFS-BFS based synthesis algorithm that reduces the computation time compared to the DFS method and requires less space compared to the BFS method, while optimizing the cost of the circuit. Synthesis results on several reversible benchmark circuits have been reported.

At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed. In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs.

Reversible circuits build the basis for emerging technologies like quantum computation and have promising applications in domains like low power design. Hence, much progress in the development of design solutions for this kind of circuits has been made in the last decade. In this paper, we provide an overview on reversible circuits as well as their applications. We discuss recent accomplishments and, finally, have a look on future challenges in the design of circuits for this emerging technology.