Optimized reversible arithmetic logic units

Reversible logic is emerging as a promising alternative for applications in low-power design and quantum computation in recent years due to its ability to reduce power dissipation, which is an important research area in low power VLSI and ULSI designs. Many important contributions have been made in the literatures towards the reversible implementations of arithmetic and logical structures; however, there have not been many efforts directed towards efficient approaches for designing reversible Arithmetic Logic Unit (ALU). In this study, three efficient approaches are presented and their implementations in the design of reversible ALUs are demonstrated. Three new designs of reversible one-digit arithmetic logic unit for quantum arithmetic has been presented in this article. This paper provides explicit construction of reversible ALU effecting basic arithmetic operations with respect to the minimization of cost metrics. The architectures of the designs have been proposed in which each block is realized using elementary quantum logic gates. Then, reversible implementations of the proposed designs are analyzed and evaluated. The results demonstrate that the proposed designs are cost-effective compared with the existing counterparts. All the scales are in the NANO-metric area.

Design of integrated reversible fault-tolerant arithmetic and logic unit

Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK latch, the T latch and the SR latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible latch to realize the designs of the Fredkin gate based asynchronous set/reset D latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

Reversible logic is an emerging area of research, having applications in nanotechnology, low power CMOS design, quantum computing, and DNA computing. In this paper, two different parity-preserving reversible error coding and detection circuits are studied. First we propose two new reversible Hamming code generator circuits. One of them is parity-preserve. We also propose a new parity-preserving reversible Hamming code error detector circuit. The proposed parity-preserving reversible Hamming code generator (PPHCG) and error detector circuits provide single error correction–double error detection (SEC–DED). The designs are better than the existing counterparts in terms of quantum cost (QC), number of constant inputs, and number of garbage outputs. Then we propose parity-preserving reversible cyclic code encoder/decoder circuits for the first time. A parity-preserving reversible D flip-flop is also proposed. Equivalent quantum representation of two parity-preserving 4 ∗ 4 reversible gates, IG, and PPHCG, are also proposed. We show for the first time that IG has a QC of only 7 and PPHCG has a QC of only 6.

In today’s electrical or electronic designing, power dissipation becomes dominant. The promising alternative to these technologies is the reversible computing. Because for irreversible circuits, information is lost and it dissipates energy as heat. The dissipated energy is proportional to the number of bits lost during computation. In case of reversible circuits, they do not dissipate energy in a large amount as irreversible circuits. So information is not lost in reversible circuits during the execution of operation. Thus generation of unique outputs from the particular inputs and reconstruction of inputs from the particular outputs can be achievable. So in the view point of designing issues, reversible logic is a promising field of research that finds applications in low power computing, quantum computing, optical computing and other emerging computing technologies, bioinformatics and nanotechnology-based systems. Here, an approach for the designing of optimized reversible parallel multiplier (ORPM) by reversible gates has been followed. In this regard, this paper represents a new partial reversible gate RPPG for partial product generation for the designing of ORPM. Also, two designing methods are proposed to design ORPM and a comparison is also made between these two methods and the existing reversible multiplier circuits reported in the literature in perspective of the number of reversible gates, constant input, garbage output and total logical calculation.KeywordsReversible logicReversible gateReversible parallel multiplierGarbage outputConstant inputs

Signal processing had a significant impact on the development of many elements of modern life, including telecommunications, education, healthcare, industry, and security. The semiconductor industry is the primary driver of signal processing innovation, producing ever-more sophisticated electronic devices and circuits in response to global demand. In addition, the central processing unit (CPU) is described as the “brain” of a computer or all electronic devices and signal processing. CPU is a critical electronic device that includes vital components such as memory, multiplier, adder, etc. Also, one of the essential components of the CPU is the arithmetic and logic unit (ALU), which executes the arithmetic and logical operations within all types of CPU operations, such as addition, multiplication, and subtraction. However, delay, occupied areas, and energy consumption are essential parameters in ALU circuits. Since the recent ALU designs experienced problems like high delay, high occupied area, and high energy consumption, implementing electronic circuits based on new technology can significantly boost the performance of entire signal processing devices, including microcontrollers, microprocessors, and printed devices, with high-speed and low occupied space. Quantum dot cellular automata (QCA) is an effective technology for implementing all electronic circuits and signal processing applications to solve these shortcomings. It is a transistor-less nanotechnology being explored as a successor to established technologies like CMOS and VLSI due to its ultra-low power dissipation, high device density, fast operating speed in THz, and reduced circuit complexity. This research proposes a ground-breaking ALU that upgrades electrical devices such as microcontrollers by applying cutting-edge QCA nanotechnology. The primary goal is to offer a novel ALU architecture that fully utilizes the potential of QCA nanotechnology. Using a new and efficient approach, the fundamental gates are skillfully utilized with a coplanar layout based on a single cell not rotated. Furthermore, this work presents an enhanced 1-bit and 2-bit arithmetic logic unit in quantum dot cellular automata. The recommended design includes logic, arithmetic operations, full adder (FA) design, and multiplexers. Using the powerful simulation tools QCADesigner, all proposed designs are evaluated and verified. The simulation outcomes indicates that the suggested ALU has 42.48 and 64.28% improvements concerning cell count and total occupied area in comparison to the best earlier single-layer and multi-layer designs.

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts. Keywords: Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic. doi: 10.3329/jbas.v32i2.2431 Journal of Bangladesh Academy of Sciences Vol.32(2) 2008 234-250

In recent years, there has been an increasing tendency towards designing circuits based on reversible logic, and has received much attention because of preventing internal power dissipation. In digital computing systems, multiplier circuits are one of the most fundamental and practical circuits used in the development of a wide range of hardware such as arithmetic circuits and Arithmetic Logic Unit (ALU). Vedic multiplier, which is based on Urdhva Tiryakbhayam (UT) algorithm, has many applications in circuit designing because of its high speed in performing multiplication compared to other multipliers. In Vedic multipliers, partial products are obtained through vertical and cross multiplication. In this paper, we propose four [Formula: see text] reversible Vedic multiplier blocks and use each one of them in its right place. Then, we propose a [Formula: see text] reversible Vedic multiplier using the four aforementioned multipliers. We prove that our design leads to better results in terms of quantum cost, number of constant inputs and number of garbage outputs, compared to the previous ones. We also expand our proposed design to [Formula: see text] multipliers which enable us to develop our proposed design in every dimension. Moreover, we propose a formula in order to calculate the quantum cost of our proposed [Formula: see text] reversible Vedic multiplier, which allows us to calculate the quantum cost even before designing the multiplier.

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.

The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates, which operate on qubits. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement and additionally, it is capable of detecting single bit error. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in Modelsim software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs.

Reversible logic has represented itself as a prominent technology which plays an important role in Quantum Computing. Theoretically Quantum Computers operates at high speed and consumes less power. Furthermore, Reversible logic can break the conventional speed of power trade-off. To prove this we are implementing Ripple Carry Adder and Carry Look Ahead Adder using reversible logic gates. The paper presents efficient adder circuits using Peres gate, New fault Tolerant gate and Double Feyman gate. The complexity, simulated outputs and the speed parameters for the adder circuit have been indicated using the Quartus II 9.1 edition and Modelsim tool. Moreover, the quantum algorithms can potentially solve NP-complete problems. Furthermore, doing high performance functions beyond the limit of deterministic computer systems is possible by only reversible logic. Quantum operations are unitary in nature which is reversible and hence the arithmetic operations like adders can be implemented using the reversible logic. Likewise, optimized block size, minimum ancillary bits, and one to one mappings of inputs and outputs are obtained in the reversible adder circuit, giving fan out as 1. Hence, the Ripple Carry Adder and Carry look Ahead Adder is providing complexity reduction and high speed, proving to be an efficient and important part in the development of arithmetic blocks of Quantum Computers.

Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed. The most important application of reversible logic is quantum computing. Quantum Computation cannot be performed without the use of reversible circuits. A number of reversible gates have been designed and used in quantum computing. The best way to derive the maximum out of reversible computation is to design those gates and circuits using systems which are inherently reversible. This is true for the quantum mechanical systems. For this quantum level designing Quantum-dot Cellular Automata stands as the appropriate choice. It's a nano level based archetype. Performing multiple functions using single circuits has always been the aim of the digital industry researchers. In reversible logic the approach is developing towards designing multifunction gates that can perform a number of functions using a same circuit with some adjustments. This development has however not yet been explored much in QCA. In this paper the majority logic equations for the outputs of a multifunction reversible logic gate are derived and the novel Quantum-dot Cellular Automata design is proposed. Some of the functions of multifunction reversible logic gate are discussed and simulated results using QCA Designer 2.0.3 are shown in the figure.

Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing.