A new level restoration circuit for multi-valued logic

Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width trade- offs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.

The speed and area advantage of domino logic circuits compared to static logic circuits makes them a favorite choice for the critical path of high performance processors. However they suffer from low noise margin. Noise is not scaling at the same rate as the supply voltage, and therefore new domino logic circuits are required to increase the noise margin. In this paper a new domino circuit is introduced. Simulations for a 3-input 180 nm AND gate shows that the noise margin can be increased by 62% with only 3% reduction in speed.

In complementary metal–oxide–semiconductor (CMOS) high-speed buffer design, leakage power dissipation, complex routing area, and low-power consumption are the most common challenges. To overcome these challenges, the BiCMOS technology and CMOS multi-valued logic (MVL) are used to maintain the yield and the performance of the high-speed buffers. In this paper, performance comparison of different types of buffers: Schmitt trigger, tristate and bidirectional buffer with BiCMOS and CMOS MVL logic are presented. Cadence virtuoso editor and ADE spectre simulator at gpdk 180 nm technology node are used for simulation setup. The results show that CMOS MVL logic delay, power dissipation, low and high noise margin are better than BiCMOS by 20, 43, 19, and 39%, respectively. Based on these results, CMOS MVL logic outperforms BiCMOS for low-power applications at comparable speed.

In this work, bulk negative capacitance junctionless (NCJL) transistor design is proposed as an alternative to conventional silicon-on-insulator (SOI) NCJL devices to minimize the temperature induced variations. The bulk architecture enables improved gate electrostatic control by shifting the conduction channel towards the front interface, thereby enhancing the matching between gate and ferroelectric capacitances. Through careful design optimization, results showcase that bulk NCJL transistor designed with moderate bulk doping of 7×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> achieves superior threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) stability and relatively lower subthreshold swing (S<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">swing</inf>) as compared to its SOI counterpart at elevated temperatures. The improved V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> stability translates into an enhanced noise margin (NM) along with lower NM variation in bulk NCJL inverter operation at elevated temperatures. The results underscore the outperformance of bulk NCJL transistors for low-power logic applications.

In recent years, due to the high ability of the multi‐valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi‐valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary latch has been used to store the ternary value, which has a considerably more static power and lower static noise margin in comparison to a binary latch. The proposed memory cells are based on decoding the ternary value to the binary one and saving in two binary latches; in this way, the storage power is sharply decreased and the static noise margin of the proposed ternary memory cell is also increased considerably to get close to that of a binary memory cell. The results of the simulation, using the HSPICE software and the Stanford 32 nm CNFET library with the voltage of 0.9 V, demonstrated that the proposed ternary memory cell achieved significant power saving and static noise margin improvement, as compared to the previous works with the same transistor count, which was expected.

Low-power circuit designs are required for battery-operated devices. A transistor needs to be small enough to be integrated onto a single chip. Therefore, CNTFET technology has been widely used to design nanoscale circuits for energy-efficient integration. Multiple-valued logic is utilised to reduce the circuit complexity by minimizing the interconnections. Compared to binary circuits, MVL circuits are more noise sensitive. As a result, it’s essential to consider noise margin into account when designing sustainable and reliable ternary circuits. The paper proposes a standard ternary inverter and compares noise margin, power consumption, delay, and PDP measurements with existing standard ternary inverters. The proposed STI has a 68.6% higher noise margin than the existing designs and 82%, 80%, and 91% improvements in power consumption, PDP, and delay, respectively, over existing circuits.

A high performance 1.5 micron N-well double poly, double metal CMOS process technology has been developed. The patented three transistor cell coupled with this process technology achieved a 25ns 64K high speed EPROM device (8K by 8). The memory core cell with a size of 9.5um × 14.5um was designed to take advantage of maximizing read and write capabilities independently. Seven different types of transistors were generated and optimized to make this possible. A novel interpoly dielectric structure has been developed to simplify the process technology which enhances the manufacturability. High speed (25ns) and small chip size (4.72mm × 3.82mm) were achieved by utilizing a double metal technology.

Photosensitive complementary inverters, composed of multilayered molybdenum disulfide (MoS2) and molybdenum ditelluride (MoTe2), are demonstrated for the applications that require low power consumption and excellent signal‐to‐noise ratio (SNR). The photosensitive characteristics of MoS2, along with the negligible photosensitivity of MoTe2, successfully render them applicable to the light‐to‐frequency conversion circuits that enable high SNR immunity. Under blue light‐emitting diodes (LEDs), the low noise margin and transition width for the voltage transfer characteristics in complementary inverters significantly improve from 1.29 to 1.49 V and 0.24 to 0.31 V, respectively, as compared with those of inverters in the dark. The experimental demonstration of photosensitive inverters and their electrical validations on proposed concepts, supported from SPICE (i.e., simulation program with integrated circuit emphasis) simulation, are systematically obtained, substantiating that this platform can be one of the core parts for future Internet of Things (IOT) applications, which simultaneously demand both ultralow power and robustness on security.

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

This work describes the L-band low voltage (/spl ges/1.6 V) power performance of AlGAs/GaAs heterojunction bipolar transistors (HBTs), their modeling and the design of a 2-W monolithic microwave integrated circuit (MMIC) for 3-V wireless mobile PCN applications (1800 MHz). The two-stage MMIC achieves 62% power-added efficiency (PAE) and 33 dB of linear gain, at a very small chip size of 1.2 mm/sup 2/. To our knowledge this is the best combination of power performance data for wireless applications demonstrated so far for a MMIC. The chip size is about a factor of four smaller than comparable MMIC's known before. The MMIC offers the potential both for low cost production due to small chip size, single voltage supply, and high performance at the same time.

Recent advances in optical bistability in a variety of materials and devices offer the potential for high speed operation over extended ranges of wavelength and temperature. The advantages of optoelec-tronic devices and multiple-valued logic are combined in various multistable solid-state device techniques, of which negative resistance multistability is most compatible with utilization of bistable optoelec-tronic devices. Additional stable states result from negative resistance interactions and facilitate implementation of variable radix analog and digital applications. Needed characteristics of bistable optical devices are outlined for compatibility with multiple-valued logic implementation. Multiple-valued optical logic offers synergistic potential for improved performance.

With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions. Among various types of NVMs, memristors (a.k.a. RRAM) have several advantages including their small device size, low voltage operation, high speed, and CMOS-compatible fabrication process. In this article, we propose a new 8T1R RRAM-based non-volatile SRAM (NV-SRAM) which adds non-volatility to the SRAM with minimum impact on the Write and Read operations. Simulation at cell-level and array-level have confirmed that the new design performs Read and Write operations at a compatible delay, energy and noise margin as the conventional 6T SRAM, and it is among the best of all reported RRAM-based NV-SRAM designs to our knowledge. In addition, since our 8T1R design uses only one RRAM device per cell, the energy required for storing/restoring the SRAM data to/from the RRAM is significantly reduced by 60%/70% compared to the lowest storing/restoring energy of the previously proposed RRAM-based NV-SRAM designs.

A low retention Vmin 6T-SRAM is realized in 40nm CMOS technology under source bias condition. A high density (HD), ultra-low leakage (ULL) 6T SRAM cell with an area of 0.242um2 is used. We could reduce the retention Vmin of SRAM array to 0.6V using adaptive source bias scheme. Source bias is applied to achieve ultra-low leakage during standby mode of operation. Source bias results in loss of stability due to reduced effective rail-to-rail voltage of memory cell and hence becomes difficult to reduce the retention Vmin of SRAM. An adaptive source bias scheme is used to apply reduced source bias selectively for low retention noise margin (RNM) conditions. We could reduce the retention Vmin by 100mV to 0.6V compared to 0.7V realized with the conventional scheme. We could reduce the leakage at FF/125°C by 30 percent due to reduction of Vmin from 0.7V to 0.6V. At TT/0.6V/25°C, we could achieve the target leakage of 0.5pA/Cell during standby mode of operation.

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

In this paper, we propose and simulate a multifunctional transistor that exhibits device reconfigurability and realizes both nFET and pFET electrical characteristics when adequately biased. The use of this device will significantly reduce the transistor count in realizing sequential and combinational circuits and will result in highly compact design. The device uses a dual fin structure having a single mid-gap workfunction gate (\(\sim \)4.65 eV) alongside dual metal (metal-silicide) drain regions. It employs n+/p+-i junctions at the source-channel interface along with the Schottky junctions at the channel-drain interface. In practice, metal-silicides such as erbium/ytterbium silicide (ErSix/YbSix) for the n-drain and platinum silicide (PtSi) for the p-drain can be used as they provide smallest electron and hole Schottky-barrier heights (SBHs). Simulations carried out using calibrated parameters show better drive current (≈ 10− 2 − 10− 3A/μ m) compared to the quantum tunneling current in simulated state-of-the-art multifunctional devices (≈ 10− 4 − 10− 5A/μ m). In addition, butterfly curves show symmetric high (NMH) and low (NML) noise margins of 0.43V and 0.29V for zero and finite SBHs, respectively. The switching characteristics is shown to have an overshoot of \(\sim \)0.15 V for realistic SBHs which is then eliminated for the case of zero SBHs. In the last section, it is also demonstrated that a simplified structure having single mid-gap workfunction (\(\sim \)4.65 eV) drain of Nickel silicide (NiSi) does not hamper the reconfigurability of the device.