Low-power adiabatic sequential circuits with complementary pass-transistor logic

The present paper proposes the comparative power analysis of different logic gates using conventional CMOS Designs and adiabatic clock gating based designs. For achieving high performance, Adiabatic logic gates are designed using CPAL (complementary pass transistor adiabatic logic).The design of INVERTER, NAND and XOR has been simulated and verified. All the circuits have been simulated using 90nm technology. In comparison to conventional CMOS designs, adiabatic technology based designs consumes much less power and saves energy.

An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic (CSCPAL) operated by four phase power clock is proposed. It realizes low switching noise and incurs low leakage power. FinFETs are ideal devices for low power circuit design due to their enhanced properties of reduced short channel effects and lower leakage current. The circuits are designed using 32nm FinFET models and are simulated using Cadence® Virtuoso design tools. Efficiency of FinFET based CSCPAL is compared with FinFET based 2N2N2P, 2N2P and PFAL designs found in the literature. Energy consumption of CSCPAL Inverter/Buffer, AND and XOR sub modules used in the design of 8-bit Carry Lookahead Adder circuits have been compared with the 2N2P, 2N2N2P and PFAL based circuit counterparts. 8-bit CLA is taken as a benchmark circuit for validation of energy efficiency.

Adiabatic logic circuit can be considered as one of the most attractive solutions for low power circuits. This paper treats a design optimization of Two-Level Adiabatic Logic (2LAL) circuit which has a relatively simple structure and an excellent low-power performance compared with many other asymptotically adiabatic or quasi-adiabatic logic families, while it needs a large number of timing buffers for "decomputation". We focus on "early decompute" technique for fully pipelined 2LAL, and proposes an ILP approach to the optimization of early decompute for minimizing hardware cost. First we show that our hardware minimization problem can be reduced into "Stable Set" problem, and then we derive its ILP formulation. The superiority of the proposed method is evaluated using ISCAS-85 benchmark circuits.

A novel fast true single phase clocking (TSPC) adiabatic differential logic circuit using dynamic threshold (DTMOS) is proposed (DT-TSPC-A). It is capable of operating at 0.7 V. The performance of four circuit architectures (DT-TSPC-A, conventional static CMOS logic, and two other published adiabatic circuits) is compared using a four inverter chain as the test circuit. At 50 MHz and 0.8 V with 20 fF load, this circuit consumes the least amount of energy of the four circuit architectures compared. It takes about the same area and consumes 55% less energy than the static circuit. It has the shortest delay and is 56% faster than other adiabatic circuits and takes at most 2.3 times the area. In addition results for more complex circuits are supplied demonstrating the improved performance of DT-TSPC-A circuits.

Multiple-valued logic has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. Lowenergy (adiabatic) logic circuits have also been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional DC power supply, these adiabatic logic circuits use ‘AC’ power supplies (power clocks) that allow energy recovery and also serve as timing clocks for the logic. In this paper we describe the adiabatic operation of a quaternary logic circuit.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.

This paper discusses the behavior of three popular adiabatic logic architectures, namely, Transmission-Gate based Adiabatic Logic, Efficient Charge Recovery Logic and static CMOS logic, in deep-submicrometer nodes. Comparison among their energy consumptions is done for varying rise times of the power supply, and for varying channel lengths, and the role of leakage current is studied. It is found that due to subthreshold leakage, adiabatic logic circuits may consume more power than conventional CMOS circuits, as channel lengths decrease.Thus it is recommended that for 90 nm technology node, channel lengths of greater than 200 nm must be used for adiabatic logic circuit implementations. It is also found that transmission-gate based logic circuits consume much less power compared to the other adiabatic logic styles.

A new pass-transistor logic called the current-sensing complementary pass-transistor logic tree (CSCPTL) is proposed and investigated. The new logic circuit can be used in low-voltage low-power systems for high-speed applications. To examine the low-voltage applications, a 1.2 V supply voltage is selected for one battery back-up systems. The current-sensing scheme yields a good sensing speed with small voltage swing. The dc power dissipation of the current mode circuit makes it difficult to apply in low power applications. The new circuit can resolve the dc power problem in the current-sensing scheme. The new circuit has superior speed performance with a power-delay product comparable to LCPL which is acknowledged to have the most potential in low-voltage low-power digital circuits design. The CSCPTL can be operated at 1.2 V without changing the conventional 5 V CMOS process.

Logic circuits in digital electronics can generally be classified two categories-combinational and sequential logic circuits.There are several software-based applications and hardware description languages to describe the structure and behavior of electronic circuits.Although it is an easy to construct a state transition table from the state transition diagram,creating an excitation table according to the memory element type in the sequential circuit design is a very laborious and time-consuming task.After the logic functions extracted from the state transition tables are obtained,logic design verification can be carried out by a conventional simulator.This will require time and persistence much like learning any other skill.Computer science degrees include courses focused mainly on programming languages.There’s a strong case to be made for use of skills acquired in programming courses to shorten the learning curve.Thus, this work has proposed a method for the implementation of the circuit only the state equations of the sequential circuit without dealing with excitation tables.This eliminates the process of constructing the circuit schematically, since it does not require flip-flop selection.In this method, since the state equations can be expressed through buttonbox,checkbox,textbox etc.which are the basic elements of the programming language,the behavior of the circuit can be observed in a very short time.

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

A 64-bit low threshold voltage conditional carry adder using complementary pass-transistor logic for low-voltage and high-speed application was presented. The improved conditional sum addition rule can reduce the number of internal nodes and multiplexers in the adder design. And reducing the threshold voltage increases the speed of operation. Thus, a low threshold voltage design is favourable for implementing low-voltage, high-speed arithmetic systems. The performances of such circuits are compared with that of normal and zero threshold voltage schemes; the proposed circuit gets the lowest power-delay product and energy-delay product from 1.0V to 2.5V. The circuit is demonstrated to balance between power consumption and performance effectively.

A new FinFET-based adiabatic NAND logic circuit with Self-Adjustment of Rail Potential (SARP) is proposed. The proposed logic provides reduced power consumption when compared to conventional CMOS and adiabatic circuits. A new FinFET-based adiabatic logic is implemented based on Complementary Energy Path structure. The proposed design reduces the second-order effects, short-Channel effects occurring in Conventional CMOS circuits. The performance of the proposed SARP-FinFET-based adiabatic NAND gate is dominant when compared to the SARP-CMOS-based adiabatic NAND gate. The proposed adiabatic circuits are designed using double gate FinFET using predictive technology models (PTM) in 32 nm Technology using Synopsis HSPICE. The experimental results for the proposed adiabatic FinFET design demonstrate their effectiveness with energy consumption and power optimization.