Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation

Reports a novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique., Using the ADTPT technique to dynamically control the body bias of the pass-transistor via only one auxiliary transistor, the new SOI CMOS complementary pass-transistor logic (CPL) circuit provides superior speed performance at a low supply voltage as compared to the conventional pass-transistor logic circuits without the ADTPT technique as verified by the MEDICI simulation results. The ADTPT technique is especially effective for use in CPL circuits with serially-connected multiple inputs.

Pass Transistor Logic (PTL) has attracted more and more interest during recent years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, performance and power consumption. Existing automatic PTL synthesis tools use a direct mapping of (decomposed) BDDs to pass transistors. Thereby, structural properties of BDDs like the ordering restriction and the fact that the select signals of the multiplexers (corresponding to BDD nodes) directly depend on input variables, are imposed on PTL circuits although they are not necessary for PTL synthesis. General multiplexer circuits can be used instead and should provide a much higher potential for optimization compared to a pure BDD approach. Nevertheless-to the best of our knowledge-an optimization of general Multiplexer Circuits (MCs) for PTL synthesis has not been tried so far due to a lack of suitable optimization approaches. In this paper we present such an algorithm which is based on efficient BDD optimization techniques. Our experiments prove that there is indeed a high optimization potential by the use of general MCs-both concerning area and depth of the resulting PTL networks.

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. It can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4-bit multiplier proved that 70% power dissipation reduction was achieved, with 30% area overhead, and no reduction in the circuit speed.

A new low-power design method based on multiple low swing internal voltage values is proposed in this paper. The proposed technique can be applied in logic circuits, which are designed with different logic family techniques such as Complementary Pass Transistor Logic (CPL), Domino Logic and Cascade Voltage Switch Logic (CVSL). The goal of this method is the reduction of the circuit power dissipation, with only a negligible increase in the area, and without a reduction in the circuit operating speed. This is achieved with the replacement of a number of selected full swing voltage circuit components by low swing voltage components. The application of the proposed technique in a CPL 4 bit multiplier proved that 30% power dissipation reduction was achieved, with 5% area overhead, and no reduction in the circuit speed.

Most digital logic circuits in silicon films deposited on sapphire substrates

Dynamic logic circuits are preferred over CMOS static logic circuits due to the low area and high-speed advantage they offer in high-performance designs. In electronics circuits, the power dissipated by the clock plays a crucial role, and hence research approach in this paper is predominantly centered on the examination of the dynamic logic circuit's comparative performance. This presented work uses the tanner tool to present a novel phase detector (PD) and phase-frequency detector (PFD) using dynamic logic architecture in standard 250nm and 45nm technology. The presented approach optimizes the circuit's speed and power by customizing the conventional approach. The transistor count has been dropped, resulting in lower power consumption and a smaller layout. All the circuit performances like transistor delay, power dissipation, the figure of merit has been optimized. Optimized results are glitch-free and enhance the performance of the circuit. The power supply voltage Vdd is varied in the range of 0.6-1.4 volts and the W/L value for PMOS and NMOS is varied within 1 and 5 to analyze its power and delay performances. These results presented the best possible trade-off between the proposed design in comparison to other existing techniques to optimize area, power, and speed for VLSI circuits.

This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have L/sub eff/=0.15 /spl mu/m. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about 2.2 times that of a partially-depleted device at the same bias. We compared three differential static CMOS topologies: (a) standard CMOS logic; (b) push-pull cascode logic (PPCL), a low power high speed static logic topology; (c) complementary pass-transistor logic (CPL), known for its efficiency for device use and popular for fast arithmetic operations. We considered three cases: (a) partially-depleted device with standard bulk-like connection where the body is tied to the supply rail; (b) partially-depleted device with floating body (FB); (c) dual gate (DG) device where the bottom gate is driven with the top gate simultaneously. Based on a methodology described previously (Tretz et al. Proc. IEEE Midwest Symp. on Circuits and Systems, pp. 179-82, 1996), performance comparison of these topologies is sufficient to establish the relative performance of almost any other differential static CMOS topology, using the generic differential CMOS static gate concept. All differential static circuits can be described as a variation of the generic differential static gate comprised of pull-up and pull-down switches, cross-coupled elements, additional resistive loads, and active paths to V/sub dd//GND.

A new pass-transistor logic called the current-sensing complementary pass-transistor logic tree (CSCPTL) is proposed and investigated. The new logic circuit can be used in low-voltage low-power systems for high-speed applications. To examine the low-voltage applications, a 1.2 V supply voltage is selected for one battery back-up systems. The current-sensing scheme yields a good sensing speed with small voltage swing. The dc power dissipation of the current mode circuit makes it difficult to apply in low power applications. The new circuit can resolve the dc power problem in the current-sensing scheme. The new circuit has superior speed performance with a power-delay product comparable to LCPL which is acknowledged to have the most potential in low-voltage low-power digital circuits design. The CSCPTL can be operated at 1.2 V without changing the conventional 5 V CMOS process.

This paper presents the realization of multiple-valued flip-flops (MVFF) using pass transistor logic. Realization of MVFF has been discussed by many authors. The existing techniques are mainly extensions of binary flip-flops, based on CMOS or TTL logic. We propose here, two different design techniques for MVFF realized by pass transistors, which can be a promising alternative to static CMOS for deep sub-micron design. We have introduced a circuit consisting of multiple valued pass transistors which we call 'logical sum circuit'. This particular circuit is used as the elementary design component for our second approach in MVFF design. Our proposed MVFF circuits can be attractive for its inherent lesser power and component demands in comparison with existing techniques using MOS or TTL logic.

The construction of DNA logic circuits is the basis of DNA computers. DNA origami has nanoscale spatial addressability, which provides an ideal framework for the construction of DNA logic circuits. Here, we propose a strategy for constructing DNA logic circuits based on a DNA origami substrate. First, hairpin DNA strands are anchored on a DNA origami substrate to form a DNA wire track. Then, we design three different output ends for different logic circuits (AND, OR and NAND). The operations of the logic circuits are completed on the DNA wire track through the proximal hairpin circuit cascade. Finally, the results of the logical operation are determined by fluorescence detection. We use this strategy to construct two-input AND, OR, and NAND gates on a DNA origami substrate, and then extend this strategy to the construction of large-scale logic circuits and functional combinational logic circuits.

We present a new mixed pass-transistor logic (PTL) and static CMOS logic synthesis method based on a genetic search. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/CMOS logic gates using BDDs. The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay or power consumption or both in a 0.25 /spl mu/m CMOS process. The average area, power consumption, and power-delay product of ISCAS85 and MCNC91 benchmark circuits using the proposed method are 25%, 40%, and 45% better than their static counterparts, respectively.

In this work, with the aid of a short-channel SPICE model, we evaluate the circuit performance of 2D negative-capacitance FETs (2D-NCFETs) considering the impact of spacers. Although high-k spacer may introduce parasitic capacitance, our study indicates that using higher-k spacer may improve the circuit performance for 2D-NCFETs due to the enhanced negative-capacitance effects (NC effects). In addition, considering the NC amplified gate capacitance, the intrinsic delay of 2D-NCFETs is still better than that of 2DFETs, especially for pass-transistor logic (PTL).

The speed and area advantage of domino logic circuits compared to static logic circuits makes them a favorite choice for the critical path of high performance processors. However they suffer from low noise margin. Noise is not scaling at the same rate as the supply voltage, and therefore new domino logic circuits are required to increase the noise margin. In this paper a new domino circuit is introduced. Simulations for a 3-input 180 nm AND gate shows that the noise margin can be increased by 62% with only 3% reduction in speed.

Profuse dendritic-synaptic interconnections among neurons in the neocortex embed intricate logic structures enabling sophisticated decision-making that vastly outperforms any artificial electronic analogues1-3. The physical complexity is far beyond existing circuit fabrication technologies: moreover, the network in a brain is dynamically reconfigurable, which provides flexibility and adaptability to changing environments4-6. In contrast, state-of-the-art semiconductor logic circuits are based on threshold switches that are hard-wired to perform predefined logic functions. To advance the performance of logic circuits, we are re-imagining fundamental electronic circuit elements by expressing complex logic in nanometre-scale material properties. Here we use voltage-driven conditional logic interconnectivity among five distinct molecular redox states of a metal-organic complex to embed a 'thicket' of decision trees(composed of multiple if-then-else conditional statements) having 71 nodes within a single memristor. The resultant current-voltage characteristic of this molecular memristor (a 'memory resistor', a globally passive resistive-switch circuit element that axiomatically complements the set of capacitor, inductor and resistor) exhibits eight recurrent and history-dependent non-volatile switching transitions between two conductance levels in a single sweep cycle. The identity of each molecular redox state was determined with in situ Raman spectroscopy and confirmed by quantum chemical calculations, revealing the electron transport mechanism. Using simple circuits of only these elements, we experimentally demonstrate dynamically reconfigurable, commutative and non-commutative stateful logic in multivariable decision trees that execute in a single time step and can, for example, be applied as local intelligence in edge computing7-9.