Device engineering for stable and reliable gate operation in Schottky-type p-GaN gate HEMTs

We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (Vth) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the Vth raises from −0.67 V to −0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage.

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction)whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> , proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> for ten years lifetime was extrapolated to be -5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V VDS OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = -5.5 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = 0 V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system.

Recently, p-GaN gate high electron mobility transistors (HEMTs) have emerged as competitive participants for next-generation high-performance power supply applications. However, the threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) instability caused by short-circuit events jeopardizes the overall reliability of p-GaN gate HEMT and the power system in real applications. Hence, a noninvasive condition-based monitoring technique for critical device parameters is urgently required to enhance system safety without affecting the features of power electronic systems. In this paper, the threshold voltage instability dynamics of p-GaN gate HEMT under repetitive short stress were investigated to achieve high estimation accuracy and good monitoring efficiency. A double-phase adaptive neural network to predict the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> degradation kinetics based on the historical degradation recordings of the target device is developed. The degradation process contains a monotonous increasing process and an oscillation process divided by random changing point subject to Weibull distribution. Based on such characteristics, the extreme learning machines were combined with classic activation functions and periodic activation functions to predict the threshold voltage tendencies of p-GaN HEMTs under repetitive SC stress. The experiment results validate that the developed model based on static investigations can provide degradation predictions with high accuracies. Besides, the proposed method endows substantial benefits for the conditional-based monitoring problem of other newly emerging semiconductor devices that feature multiple scenarios during the dynamic process and differences between individual units.

We have evaluated specific on-state resistance (Ron,sp) and switching performance of various GaN power field-effect transistors (FETs) with 600 and 1200 V ratings using analytical calculation and numerical simulation. The normally-off GaN power FET family includes lateral p-GaN gate high electron mobility transistors (HEMTs), lateral metal-oxide-semiconductor (MOS) channel HEMTs, current aperture vertical electron transistors (CAVETs) and vertical U-shaped trench-gate MOS field-effect transistors (UMOSFETs). This study shows the advantages of vertical GaN power FETs over lateral GaN power HEMTs. These advantages include lower Ron,sp and smaller switching energy loss, especially at higher blocking voltages (1200 V). At 600 V, lateral P-GaN gate HEMTs are competitive with vertical power FETs. Vertical GaN CAVETs perform better than both lateral HEMTs and vertical UMOSFETs at both voltage ratings, benefiting from its lowest Ron*QG figure-of-merit.

Titanium disilicide/copper (TiSi2/Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) with low gate leakage current are demonstrated. The TiSi2/Cu gate devices demonstrate electrical characteristics that are comparable to those of conventional Ni/Au gate devices. At gate voltage of −20 V, typical gate leakage current for a TiSi2/Cu gate device with a gate length of 5 μm and width of 200 μm is found to be as low as 5.15 × 10−7 mA mm−1, which is three orders lower than that of the Ni/Au gate device. The lower gate leakage current is primarily caused by the higher Schottky barrier height of TiSi2/Cu on AlGaN/GaN HEMTs than that of Ni/Au by 0.36 eV. The threshold voltages of the TiSi2/Cu gate HEMTs were maintained to be equivalent to that of the Ni/Au gate device. No Cu diffusion was found at the metal and AlGaN interface by secondary ion mass spectrometry and scanning transmission electron microscopy. These results indicate that TiSi2 is a good barrier layer of Cu diffusion, and titanium disilicide/copper is a promising candidate for high-performance AlGaN/GaN HEMTs.

In this paper we report the first monolithic integration of InGaAs/InAlAs resonant tunneling diode (RTD) and high electron mobility transistor (HEMT) epitaxially grown on an InP substrate. The transconductance for a 1- mu m gate HEMT was 400 mS/mm and the peak-to-valley current ratio of the RTD was 3.1. Using this integrated structure, we demonstrate a static RAM cell circuit, consisting of a single transistor with two RTDs on the transistor. The memory cell circuit exhibits bistability, based on the RTD's negative differential resistance (NDR), at supply voltages from 0.6 to 1.1 V.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The low ionization rate of Mg acceptors in the p-gallium nitride (GaN) layer is a critical factor accounting for the low current density of E-mode GaN p-FETs. In this work, polarization-enhanced technology was adopted to enhance the ionization rate of the p-GaN channel. High-performance recessed-gate E-mode GaN p-FETs were fabricated to enable GaN complementary logic (CL) circuits. During fabrication, the channel thickness (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub>) is found to be a critical parameter that influences the device metrics. With a decrease in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> (i.e., larger recess depth), a more negative threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub>) is achieved; however, the trade-off is an increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula>. The E-mode GaN p-FET with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> = 32 nm exhibits a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of -1.1 V, a high current density of 17.7 mA/mm, a high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{on}}$</tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{I}_{\biosc{off}}$</tex-math></inline-formula> of 6.9 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>7</roman></sup>, and a low subthreshold swing (SS) of 93 mV/dec. Furthermore, an E-mode n-channel p-GaN gate high electron mobility transistor (HEMT) was fabricated on the same epi-wafer, exhibiting a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>th</roman></sub> of 1.3 V and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\textit{R}_{\biosc{on}}$</tex-math></inline-formula> of 6 <roman xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ω⋅</roman>mm. Finally, a GaN CL inverter was fabricated and demonstrated under <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>DD</roman></sub> = 6 V. Rail-to-rail voltage swing and low static power consumption were both achieved. This work further validates the feasibility of GaN CL integrated circuits and power integrated circuits (PICs).

AlGaN/GaN high electron mobility transistors (HEMTs) are promising candidates for high power and high current applications with its high mobility and high breakdown field. Epitaxial films for device substrate are typically grown on sapphire or silicon carbide, SiC, with dislocation densities in the order of 108 - 1010cm-2 due to their thermal coefficient and lattice mismatches. The thinner GaN buffer layers on SiC have been reported to have higher threading dislocation density in the GaN, but lead to higher off-state breakdown voltages. However, thick GaN buffer layers on sapphire and their impact on dc performance have not been widely studied. In this study, the impact of GaN buffer layer quality on dc and gate-lag pulse performance of AlGaN/GaN HEMTs was studied. Transmission electron microscopy (TEM) was used to measure the dislocation density in the GaN buffer layer of the HEMT samples. Dc characteristics, including drain I-Vs, transfer characteristics, and gate pulsed drain I-V characteristics of the HEMTs, were measured to establish a correlation between the AlGaN/GaN HEMTs’ dc and gate-pulsed performance and GaN buffer layer quality. AlGaN/GaN HEMT structures grown by metal organic chemical vapor deposition (MOCVD) on sapphire substrates were acquired from two different vendors. Both types of wafers had 24% Al concentration in the AlGaN barrier layer. One type of wafer had a 5 µm GaN buffer and the other had a 2 µm GaN buffer layer. HEMT fabrication was started with mesa patterning by conventional optical lithography. The mesa-etching was achieved using a unaxis shuttle-lock reactive ion etcher with inductively coupled plasma module (ICP) for device isolation with a Cl2/Ar plasma. Ohmic metallization of electron-beam evaporated Ti/Al/Ni/Au (25 nm/125 nm/45 nm/100 nm) was patterned by lift-off and subsequently rapid thermally annealed at 850⁰C in a flowing N2 ambient for 45 seconds. Schottky gates of e-beam evaporated Ni/Au (20 nm/80 nm) with 100 μm width and 1 μm length were obtained by standard lift-off patterning. DC current–voltage (I-V) characteristics were measured using an HP4156 parameter analyzer, and gate-lag pulse measurements were measured using an Agilent 8114A pulse generator. Figure 1 shows the bright field cross-sectional transmission electron microscopy (BF-XTEM) pictures of AlGaN/GaN surface for the top layers of (a) HEMT structure with 2 µm GaN buffer layer, (b) HEMT structure with 5 μm GaN buffer layer as well as the GaN/sapphire interface for the (c) HEMT structure with 2 μm GaN buffer layer, and (d) HEMT structure with 5 μm GaN buffer layer. Dislocations are seen to originate near the GaN/sapphire interface and propagate up through the AlGaN/GaN interface to the surface of both HEMT wafers. However, it is clear that the HEMT structure with 2 μm GaN buffer layer exhibited a much higher defect density. The calculated defect density for 2 μm GaN buffer layer substrate had an order of magnitude higher defect density. However, 5μm GaN buffer layer wafer showed that it was under high strain with larger height difference across the 2 inch with lower radius of curvature. There was no major difference in HEMTs’ dc performance was observed. In the other hand, Figure 2 (a) and (b) shows that gate lag measurement on fabricated HEMTs on 5 μm GaN buffer layer wafer showed no degradation and on 2 μm GaN buffer layer wafer showed the otherwise. The effects of defect density on HEMT dc and radio frequency performance were studied. HEMTs were fabricated on 2 and 5 μm of GaN buffer layers with the same composition of active layers. Despite there was no significant difference was seen in dc characteristics, significant reduction in pulse measurements was observed on thinner GaN layer HEMTs. These results suggest that the defects created in GaN buffer layer do not largely influence device dc performance but are closely related to high frequency performance. Figure 1

Compared with silicon, GaN has advantages such as high electron mobility large band gap and high breakdown field strength. Therefore, GaN High Electron Mobility Transistors (HEMT) is resistant to high voltage and high temperature, and GaN HEMT performs well in high-frequency and high-power fields. Enhancement mode GaN HEMT is more suitable for most applications than depletion mode GaN HEMT due to enhancement mode GaN HEMT’s normally-off characteristic. This paper introduces cascode structure GaN HEMT and p-GaN gate structure GaN HEMT, as well as two improved structures, monolithically integrated Si-GaN cascoded FET and Hybrid Drain embedded Gate Injection Transistor, then compares the four structures and analyzes the advantages and disadvantages. Because of the unique advantages of GaN HEMT, many industries that require the use of high-frequency devices or high-power devices are very interested in the application research of GaN HEMT. This paper mainly introduces the research progress of GaN HEMT’s application in the three fields of radio frequency amplifiers, charger circuits, and LiDAR drivers, and the paper summarizes the advantages and current challenges of GaN HEMT, as well as the future of GaN HEMT’s development and application.

In this paper, we present our recent research on the demonstration of normally-OFF operation and high-performance device merits in GaN high electron mobility transistors (HEMTs), which are enabled by the employment of thin-barrier AlGaN/GaN heterostructures. Two types of thin-barrier HEMTs are investigated: one is with a metal–oxide–semiconductor (MOS) gate structure, and the other is with a p-GaN gate stack. The MOSHEMTs feature an as-grown thin-barrier heterostructure with a gate-recess-free fabrication process and a high-k ZrO2 gate dielectric. Approaches including selective area barrier regrowth and selective area surface passivation are implemented to minimize the access resistance in the MOSHEMTs. For the p-GaN gate HEMTs, a T-shaped Schottky gate contact scheme is employed to realize superior gate stack reliability. Normally-OFF operation with a large threshold voltage ⩾1.5 V, a high maximum drain current ⩾450 mA mm−1, a steep subthreshold slope ⩽95 mV dec−1, and negligible hysteresis are achieved in all the demonstrated device structures. Moreover, in analyzing the reported device results with the corresponding heterostructure design, we discuss the benefits and tradeoffs of thin-barrier MOSHEMTs and p-GaN gate HEMTs, respectively.

This study explores gate reliability in p-GaN high electron mobility transistors (HEMTs) using different gate stack engineering (GSE) techniques. It analyses normally-off HEMTs with p-GaN gates, fabricated with varying Mg doping concentrations and an additional stack between the Schottky gate metal and p-GaN region. The analysis is based on device characteristics like threshold voltage (V TH), On-state resistance (RDS-ON), and gate breakdown (G<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</inf>). Also, a novel approach, the successive multi-stage compliance ramp voltage sweep (MSC-RVS) methodology, is employed to investigate forward gate breakdown mechanisms. MSC-RVS allows the observation of various gate BD mechanisms associated with GaN in a single short-duration stress test. This involves gradually increasing gate current compliance (ICOMP) and repeatedly initiating multiple BD events through a ramped voltage sweep along the Schottky, Passivation, and PiN regions. These comprehensive studies on p-GaN gate performance, utilizing diverse GSE approaches, offer deeper insights into achieving high gate reliability for p-GaN gate HEMTs.

Background and Objectives: High electron mobility transistors (HEMTs) are designed so that they are able to work at higher frequencies than conventional transistors and this has made them an attractive topic of research.Methods: Two developed designs of InGaAs/InAlAs high electron mobility transistors have been studied. The proposed laterally contacted HEMTs satisfy the desired high frequency characteristics and are good candidates for high frequency applications. Two kinds of HEMTs have been designed and simulated: single-gate laterally contacted HEMT (SGLC-HEMT) and doublegate laterally contacted HEMT (DGLC-HEMT).Results: The proposed SGLC-HEMT exhibits 111 GHz current-gain cut-off frequency. By using double-gate design, the current-gain cut-off frequency has been increased to 256 GHz. The simulation results show that the maximum oscillation frequency for the proposed SGLC and DGLC HEMTs, are 410 GHz and 768 GHz, respectively. The maximum value of transconductance (gm) for SGLC-HEMT is obtained 620 mS/mm while it is 1130 mS/mm for DGLC-HEMT.Conclusion: In order to increase the fT and fmax, instead of decreasing the gate length which is a restricted solution because of short channel effects, a very efficient structure was proposed. The designed HEMT benefits from laterally source and drain contacts. The results showed superior performance of the laterally contacted HEMTs compared to top contacted ones. The best frequency response was obtained for DGLC-HEMT. The proposed DG-HEMT design could improve the current-gain cut-off frequency and maximum oscillation frequency to 256 GHz and 768 GHz, respectively. The comparison of the performance of the DGLC-HEMT with SGLC-HEMT and with previously reported double gate HEMTs, verified the significant improvements in DC and AC characteristics of the HEMTs caused by the proposed design.

A p-GaN gate high electron mobility transistor with the buffer avalanche triggered layer (BATL-HEMT) is experimentally demonstrated to exhibit repetitive avalanche-like behavior. One of the major limitations of conventional HEMTs is their limited avalanche capability, primarily due to the absence of an efficient removal path for the holes generated during avalanche breakdown. The local accumulation of these holes can indirectly induce severe thermal degradation, ultimately leading to potential device failure. However, in the proposed device, the unique P++P−−N++ structure initiates an avalanche effect within the buffer layer, thereby activating the established hole energy dissipation pathway. Under multiple repeated breakdown testing, the device can instantaneously dissipate high current densities without observable thermal degradation. Additionally, temperature-dependent breakdown measurements show that the BATL-HEMT exhibits a positive temperature coefficient characteristic of avalanche breakdown.

Nonlinearity operation and early gain suppression limit the high-frequency operation of GaN-HEMTs. Nonlinear transconductance and resistance drop-off at relatively large VGS are the major sources for the nonlinear operation of the high electron mobility transistors (HEMTs). In this article, we present the In0.1Ga0.9N channel-based HEMTs for stable transconductance operation. The device performance is evaluated for both Al0.3Ga0.7N, and In0.17Al0.83N barrier materials with silicon nitride passivation. The In0.17Al0.83N/In0.1Ga0.9N/GaN heterostructure device shows remarkable improvement in gate voltage swing than Al0.3Ga0.7N/In0.1Ga0.9N/GaN. LG 55 nm T-gate In0.17Al0.83N/In0.1Ga0.9N HEMT exhibited 5 A/mm of maximum drain current density (IDS, max) for 1 V gate bias, 0.72 S/mm of stable transconductance (gm,max), 43.5 V of off-state breakdown voltage (VBR), and 275/289 GHz of fT/fmax. The HEMT with AlGaN/InGaN/GaN heterostructure showed 2.81 A/mm of maximum drain current density for 1 V gate bias, 0.66 S/mm of stable transconductance, 55.3 V of VBR, and 252/263 GHz of fT/fmax. Moreover, a highest theoretical OIP3 value of 61.2 and 67.6 dBm obtained for AlGaN and InAlN barrier HEMTs, respectively. The proposed InGaN/GaN channel-based HEMTs are more reliable for high-frequency linear operation.

Near-ideal Schottky barrier contacts to n-type Al0.22Ga0.78N have been developed by a two-step surface treatment technique. Plasma etching of the AlxGa1−xN surface prior to Schottky metal deposition, combined with sequential chemical treatment of the etched surface, holds promise for developing high quality low-leakage Schottky contacts for low noise applications and for recessed gate high electron mobility transistors. In this work, the effect of postetch chemical treatment of the n-type Al0.22Ga0.78N surface on the performance of the Ni∕Au based Schottky contact has been investigated. Three different types of chemical treatment: viz, reactive ion etching, reactive ion etching plus dipping in hot aqua regia, and reactive ion etching plus dipping in hot KOH, are studied. Detailed current-voltage studies of three different surface treated diodes and a comparison with as-deposited diodes reveal significant improvement in the diode characteristics. The latter surface treatment yields Ni∕Au Schottky diodes with very low reverse leakage currents, breakdown voltages greater than 44V, and an ideality factor as low as 1.14.