Chip Alignment Templates for Multichip Module Assembly

The fan-out panel-level chip-last packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of: (a) the heterogeneous integration of one large chip and one small chip with 50µm-pitch (minimum), (b) a fine metal linewidth (L) and spacing (S) redistribution-layer (RDL)-first substrate on a temporary glass carrier, (c) an ordinary build-up package substrate on a panel, (d) a hybrid substrate which is by soldering the RDL-substrate on top of the build-up substrate, and (e) the chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis.

In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plotted into Weibull distributions, where the Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope interval and the true characteristic life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the chip/package assembly of the heterogeneous integration package are provided and discussed.

Development of a reliable flipped chip mounting technique enables demonstration of high speed, complex digital circuits. Flip chip mounting has greatly reduced parasitic inductance compared to conventional wire bonding, and permits remounting of known good die onto multi-chip modules. Superconductive digital circuits have operated to 4.3 Gb/s in our custom test station. The circuit and carrier are fabricated using TRW's foundry process. The chips are flipped onto a superconducting coplanar carrier using a low temperature solder reflow process reported on at this conference. Testing is performed in a multi-GHz, flip contact, variable temperature probe. This test facility is capable of testing circuits to 12 Gb/s. We will describe the operation and performance of our circuits at high bit rates, and design improvements intended to facilitate operation at higher bit rates with improved yield. In addition, we will discuss the use of a logic simulation tool to analyze the output words, and pinpoint the gate or gates that failed to operate properly.

Over the past two decades, 3D techniques combined with heterogeneous integration, combining different functions and materials, have emerged as a key enabler for overcoming the physical and scaling limits of traditional 2D integration. These approaches are now expanding across multiple domains, including CMOS, memories, photonics, imagers, and RF systems, with the aim of delivering next-generation integrated systems for advanced computing (AI), analog/RF, and imaging applications. In this presentation, we will explore the fundamental techniques, recent advancements, and some challenges associated with achieving integration. Special emphasis will be placed on the role of hybrid bonding and sequential 3D integration schemes, as well as their implications for energy efficiency, device performance, and system-level innovations.3D integration has transitioned from a niche research area to a cornerstone technology in microelectronics, driven by its potential to address high density interconnect and traditional 2D scaling bottlenecks for several applications and enable heterogeneous integration at unprecedented scales. At the heart of this technological evolution are advanced schemes such as wafer thinning, Through-Silicon Vias (TSVs), hybrid bonding, and sequential 3D integration techniques. These techniques have been pivotal in shrinking the interconnect length, reducing latency, and enhancing data bandwidth in computing systems. In parallel, developments in wafer-to-wafer, die-to-wafer, and chiplet integration are enabling the seamless merging of diverse materials enabling functionalities such as logic, memory, photonics, and RF. Compact form factors are achieved enabling to boost performances of the most demanding applications such as Artificial Intelligence or Tb/s transceiver applications [1].Recent studies highlight significant progress in hybrid bonding technology, which achieves high-density interconnects at the submicron scale, thereby optimizing power delivery and thermal management in stacked devices [2]. Meanwhile, sequential 3D integration [3][4] where layers of transistors are fabricated sequentially on the same substrate, is emerging as a game-changing paradigm. It promises ultra-high-density integration with minimal parasitics, creating new opportunities for energy-efficient and high-performance systems. Several applications are foreseen including C-FETS, memories and imagers [5] .Photonic interconnects will enter in next generation 3D IC integration, addressing challenges in data bandwidth, power consumption and signal integrity and enabling photonic interposers for next generation of components for data centers and communication systems [7]. Similarly, RF [8] and analog domains [9] benefit from 3D stacking by improving front-end module integration with specific materials (III-V, HR, ...), leading to enhanced performance and higher frequencies.Despite these achievements, significant challenges remain. Thermal dissipation is a critical bottleneck [10] , particularly in densely 3D stacked architectures where hotspots can severely impact reliability and performance. Moreover, the mechanical stresses induced during bonding and processing can affect device yield and long-term stability. Our recent work in advanced thermal management and stress engineering underscores the need for interdisciplinary approaches to address these challenges. Solutions such as microfluidic cooling, novel materials for thermal interface layers and specific bonding technologies are being actively explored. Furthermore, while heterogeneous integration is currently feasible at the wafer scale—such as wafer-to-wafer hybrid bonding, which is already in mass production—expanding application fields will require advancements in die-to-wafer integration techniques.Looking ahead, the convergence of 3D integration with emerging paradigms such as neuromorphic computing, quantum technologies, multispectral and smart imagers, and advanced packaging promises to redefine system design at all levels. The synergy between 3D technologies and heterogeneous integration of advanced materials, such as 2D semiconductors, III-V, ferroelectric or oxide semiconductor [11] materials, further expands the horizon for innovation.In conclusion, 3D integration has proven to be a transformative force in microelectronics, offering pathways to overcome traditional limitations and unlock new performance dimensions. Intensive researches worldwide continues contribute to push the boundaries of what is possible, paving the way for smarter, more efficient, and highly integrated systems.

Preface Acknowledgments A brief introduction to wire bonding, tape automated bonding, and flip chip on board for multichip module applications Making COB testing tractable: chip pretest and system diagnostics Chip level interconnect wire bonding for multichip modules Chip level interconnect: wafer bumping and inner lead bonding Chip level interconnect: solder bumped flip chip Chip attachment Wire bonding chip on board Tape automated bonding chip on board and on MCM-D Solder bumped flip chip attach on SLC board and multichip module Micron bump bonding chip on board chip on board encapsulation Underfill encapsulation for flip chip applications Index

Leading-edge packaging applications are demanding some combination of greater interconnect density, smaller size, higher system performance, and lower cost. The elimination of the chip-level package in favor of the direct attachment of chips to a substrate or board is an alternative that is being actively developed for many prospective applications and commercially implemented in specific situations. This multichip module (MCM) approach takes many forms depending on both the system requirements and the ever-present cost constraints. The cost/performance trade-off drives the selection of materials system: laminate board (MCM-L), multilayer ceramic (MCM-C), or deposited thin films (MCM-D). The shift to MCM technology will continue selectively, where the needs and the benefits are compelling.

We develop a high-bandwidth density organic optical multi-chip module (MCM). A high packaging density is achieved by integrating bare optical chips, developing compact fiber connectors that connect perpendicularly to the surface of the module, and manufacturing total internal reflection mirrors by a precise laser ablation technique. An assembly procedure for the optical MCM is established. It is verified that the organic MCM is resistant to heat of reflow processes and that mirror quality does not degrade due to the lens array assembly process.

The fan-out chip-last panel-level packaging for chiplets heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of a high-density organic hybrid substrate using an interconnect-layer.

This papers analyzes the ways that physical scaling of electrical interconnecting structures impacts their delays, with particular focus on multichip modules. We use for illustration example structures typical of laminate and thin-film based MCMs. Because multichip modules have higher packaging densities than conventional packaging, loading plays a correspondingly more important role in their delays. The most important parameters dominating the performance of MCMs are the average distance between the chips (i.e. the packaging density), the size of the load capacitance and the number of loads connected to the line. Focusing attention on these areas has the greatest potential to improve MCM performance, regardless of the particular substrate technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this work, IBM Research and NTK Technologies have explored the development of an organic Multi-Chip Module (MCM) solution, with the goal of developing innovative technologies that address the requirements of high performance systems. A 90 × 90 mm organic MCM was designed, fabricated, and assembled with dual side mountable 24 × 28 mm thermal test chips mounted on chip-scale interposers to enable functional screening and rework process. The work demonstrated that a large scale organic MCM was compatible with LGA sockets with over 6000 contacts.

The LSI packaging technique utilized for the SX-3/SX-X is outlined. The VLSI chip is packaged in a chip carrier called the flipped tape-automated-bonding carrier (FTC), which has 604 input/output (I/O) bumps arranged in a matrix configuration on its bottom surface. The high-density multichip package (MCP) consists of a multilayer substrate (MLS) with a maximum of 100 FTCs and 11540 I/O pins. The MLS is a 225-mm*225-mm, 5.5-mm-thick ceramic substrate with a fine-line multilayer wiring part consisting of seven polyimide insulative layers and eight conductor layers. A multilayer board mounts the MCPs with novel zero insertion force (ZIF) connectors, and high-speed coaxial cablings are used for the interconnection system. Adoption of the ZIF-MCP connector allows insertion of multiple pin sat one stroke and high-speed interconnection. A sophisticated and reliable water cooling technique is used to cool the package efficiently. Water circulates from a cooling unit (CLU) to liquid cooling modules (LCM) that cover the MCPs. This system has a cooling capacity of up to 4-kW heat dissipation of the MCP. >

In this paper a highly integrated MCP concept apply to MMICs from DC up to Ku-band is presented. This type of package of low-temperature co-fired ceramic system-in-package (LTCC-SIP) with ball grid array (BGA) structures hereby can realize miniaturization, low-weight and multifunction. More than one of the multi-function MMICs are wire-bonding or flip-chip mount on the top of multilayer LTCC substrate which was integrated all kinds of passive functions such as filter, resistance, capacitance, and the SIP can be surface mount on a PCB serving as motherboard through the via and BGA on the bottom side. The simulation and measurement for this package of the return loss return loss were −12dB at 18GHz that can meet the need of most of RF performance. And the size of the final package of the single channel RF LTCC-SIP we processed is 55mm × 20mm × 4.5mm, which is 1.4% of traditional RF module, and the package is 10g in weight, which is also 1.4% of the tradition RF module.

This paper presents the design concept and experimental results about small size radio frequency (RF) module for 5 GHz wireless local area network (WLAN). Functions of the RF module include from base band input/output to antenna switch. The size is 20 mm/spl times/15 mm/spl times/3 mm and that is minimum size in modules with same functions as far as the authors get to know. For the purpose of small size and low cost, generally known technologies are used. They are multi chip module on laminated-base dielectric substrate (MCM-L) technology, interconnection of each layer using build-up technology, flip chip technology and ball grid array (BGA) technology. Parts and ICs are on both sides of the RF module's substrate and are vertically connected in the substrate. In order to ensure electrical performance at 5 GHz frequency band in the high-density package, transmission line characteristics in the substrate and BGA characteristic are simulated by 3 dimensional (3D) electromagnetic (EM) software. The fabricated RF module is evaluated using the test set up for 5 GHz WLAN application and the result is shown.

Smart ICT (Information and Communication Technology) such as "Big Data", "Cloud computing" and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for "Edge-computing". Meanwhile MEMS/Sensors are required as multi-functionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line/space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation's build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below 10 μm with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.

Recently high-density packaging technologies have been in strong demand in an effort to realize the ubiquitous networking society. A wafer-level chip size packaging (W-CSP) technology is one of the most promising technologies for high density and environmentally-friendly packaging. The purpose of this study is to propose a fabrication method for a multichip module system using W-CSP technology. In this study, we fabricated a two-chip module with W-CSP using an excimer laser to form via-holes and electro-plating to fill the via-holes. This study has two main new technologies: one is new via-hole formation using an excimer laser that makes small (30 μm diameter) and deep (50 and 100 μm) via-holes, with a micro-lens array used to shorten via-hole formation time. The micro-lens array makes one-line via-hole formation at once. The second new technology is new copper electroplating techniques to fill the via-holes which have same diameter (30 μm) and different depths (50 and 100 μm) by controlling additives and agitating conditions. In this study, we fabricated a two-chip module, and both chips were covered by resin simultaneously. The second chip, whose thickness was 50 μm, was mounted on a wafer (first chip) after the first chip had completed the wafer process. The second chip was thinned and mounted by die attachment film (DAF). Next, the mounted chips were spin-coater with polyimide or epoxy resin about 100 μm in thickness. Two types of via-hole with different depths, 50 and 100 μ m, were formed by excimer laser to connect the wafer and mounted chip pads. Both types of via-hole had a diameter of about 30 μm. After via-hole formation, seed layers, sputtered Ti and Cu films, are necessary for subsequent copper electro-deposition. Using microscopy measurement, the seed layers were seen to be uniformly formed from the top to the bottom of the via-hole. Using a general mixture of additives, brightener, leveler, and suppressor, the via-holes were completely filled. By controlling the suppressor effect, the 100 μm deep via-holes were perfectly filled with the copper electroplating. Both mechanical agitation and current density are effective to ensure via-hole filling and optimization of these two factors is very important in filling via-holes. Moreover, an additional electroless copper seed layer to increase conductivity near the bottom of the via-hole is also effective to suppress voids there. Finally, the conductivities between the first and second chips were confirmed for the multi-chip module fabricated using W-CSP with excimer laser and copper electro-plating.