Multi-Chip Module Fabricated by W-CSP Method using Excimer Laser Via-Hole Formation and Cu Plating

A multi-chip module (MCM) was fabricated using an excimer laser driller and electro-plating. This method contributes to the interconnection properties of the MCM. First, a second chip with a thickness of 50 μm was mounted on a wafer that had been created by a wafer process, and polyimide with a thickness of about 100 μm was applied by a spin-coater to cover the mounted chips. Two types of via-holes, with depths of 50 and 100 μm, were formed by the excimer laser to connect the wafer and mounted chip pads. The excimer laser driller with a micro-lens array formed two types of via with diameters of about 30 μm simultaneously. Damage caused by the excimer laser irradiation was examined by direct laser irradiation of the FET transistor gate. Properties of the FET transistor did not change even after 500 pulses of 400 mJ/ cm 2 which is sufficient for via-hole formation. A micro-lens array was designed to shorten the via-hole formation time. After via-hole formation, a seed-layer of sputtered Ti and Cu films were necessary, followed by copper electro-deposition. Microscopy measurements confirmed that the seed-layers were uniformly formed from top to bottom of the via-hole. Generally the mixture of additives to complete the via-hole filling consists of brightener, leveler, and a suppressor. By controlling the leveler concentration, a via-hole with a diameter of 30 μm and a depth of 100 μm was perfectly filled by copper electroplating. In this way the multi-chip module was created by wafer-level chip size technologies (W-CSP) using an excimer laser driller.

In this paper, thermo-mechanical reliability of a variety of state-of-art wafer level packaging (WLP) technologies is studied from a structural design point of view. Various WLP technologies, such as Ball on I/O with and without redistribution layer (RDL), Ball on Polymer with and without under bump metallurgy (UBM) process, and encapsulated Copper Post WLPs, are investigated for their structural characteristics and reliability performance. Ball on I/O WLP, in which solder balls are attached directly to the metal pads on silicon wafer, is used as a benchmark for the analysis. 3-D finite element modeling is performed to investigate the effects of WLP structures, UBM process, polymer film material properties (in Ball on Polymer), and encapsulated epoxy material properties (in Copper Post WLP). Fundamentals underlying thermomechanical reliability mechanisms are uncovered through detailed parametric studies. Experimental tests with various parameters were conducted to validate simulation results. Both Ball on Polymer and Copper Post WLPs have shown great reliability improvement in thermal cycling. Encapsulated copper post WLP showed the best performance.

Wafer level packaging technology, as an advanced packaging technology with high maturity and wide application, has been widely used in portable products such as mobile communication. This paper mainly introduces two kinds of wafer level chip scale package forms, fan in and fan out, introduces the whole process of fan-out wafer level package and finally looks into the future development trend of wafer level chip scale package technology.

In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging fan-out wafer level packaging technologies are introduced. Several key challenges in fan-out WLP technologies are examined. Finally, Three-dimensional (3-D) integration of through-silicon-via (TSV) technology and wafer-level bonding technology with WLP, especially in MEMS and image sensor applications, is discussed.

This paper documents a chip scale package (CSP) cost analysis using SEMATECH's Cost/Resource Model (CRM). The intent of the analysis was to compare costs between CSPs and conventional package technologies such as the thin small outline package (TSOP) and ball grid array (BGA) to determine whether CSP is a viable packaging technology. The analysis includes costs of both package and board assembly components in a high volume, mature production factory. Four representative CSP types (custom lead frame, flex circuit interposer, rigid substrate interposer, and wafer level assembly) and three traditional surface mount package configurations (plastic ball grid array [PBGA], ceramic ball grid array [CBGA], and thin small outline package [TSOP]) were selected to benchmark. By selecting CSPs across many applications and I/O ranges, the goal was to study a cross section of CSPs that were in or near production. Analysis results indicated that CSPs with a low I/O count are cost-competitive with conventional surface mount packages and can be used with the existing printed circuit board (PCB) infrastructure. However, CSPs with a high I/O count are not currently supported by conventional PCB technology and are not cost-competitive with conventional surface mount package technology.

It has been several years since wafer level packaging (WLP) technology has emerged, enabling the packaging industry to successfully fabricate smaller, more reliable modules. The use of this technology is expected to continue to grow in the future. One current WLP trend is to replace high lead solder bumps with lead-free solder bumps. Two of the more promising lead-free bumps are Cu-pillars and bumps. The use of the Cu-pillar/bump approach continues to increase as fabricators drive to increase yields, create more I/O pins per wafer thus resulting in finer bump pitch. The use of liquid photoresist (PR) and/or dry film photoresist (DFR) has become the standard for fine bump pitch formation. The major challenges in using these resists are 1) the effective removal of the resist without residue or redeposit; and 2) the compatibility of the removal chemistry with under bump materials (UBM). This paper will discuss WLP market trends, the technical requirements associated with PR/DFR removal, and conclude with some experimental results of advanced PR/DFR removal.

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

An integration of 28 nm CMOS RF system with 3D solenoidal inductors (3DSI) in integrated fan-out (InFO) wafer level package technology is studied. The 3DSI provides the performance of Q-factor of 51 and isolation of −53 dB. With the 3DSI, the RF system in the InFO technology results in power saving by 58% and noise reduction by 80% in LNA and VCO, respectively, compared with those in RF SoC system. The InFO technology provides a novel solution for RF system integration.

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7×7×0.2mm) on logic EMWLP structure (die size : 8×8×0.2mm), sized 12×12×0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.

Today's consumers are looking for powerful, multifunctional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device. JCET is an industry leader in Wafer Level Packaging (WLP) technology, providing a comprehensive portfolio of WLP solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices (IPD This paper shares data and results from our labs and those of our technology partners which come from two recent tube technology advances, both show great potential for providing solutions to the issues of imaging small features quickly, faced in the higher end semiconductor manufacturing industry. Metal Jet Technology, in metal jet anode microfocus xray tubes the traditional solid metal anode is replaced with a jet of liquid metal, which acts as the electron-beam target, The metal jet supports higher electron-beam power and can therefore generate higher X-ray flux. The major benefit of the increased power density level for the metal-jet X-ray tube is the possibility to operate with a smaller focal spot, say 5 ?m, to increase image resolution and at the same time acquire the image faster, since the power is 10x higher for same spot size. Which means that a 5μm spot on a Metal Jet can tolerate approximately 5x higher power compared to a 10μm spot on a tube with a traditional solid filament This technology delivers one of the smallest and most intensive X-ray beams of any Xray source to meet the ever-increasing technology demands, including wafer level package inspection. Nano Tube Technology This enables industry-leading resolution in geometric magnification, the Nano tube is based on advanced electron optics and the latest tungsten-diamond transmission target technology. Automatic e-beam focusing, and astigmatism correction ensures that the smallest possible, truly round spot is achieved. The Nano tube also has the unique feature of internally measuring and reporting the current spot size. In addition, advanced cooling and thermal design results in extreme stability over time. This enables an unprecedented true resolution of 150 nm lines and spaces. The true round spot of the tube is demonstrated by the highly symmetric images of a ‘Siemens star’ resolution target, the innermost features are 150 nm

Introduction Within this publication micro-transfer-printing (µTP) will be introduced as a promising new technology for 3D wafer-level packaging (WLP). The main advantage of µTP arises from the substantial parallel chip transfer from the source wafer to a target device by a visco-elastic stamp. To execute and develop this versatile technology a pilot line has been installed in the X-FAB MEMS Foundry GmbH clean room facilities within a funded EU project (MICROPRINCE). To demonstrate the general process capabilities recent results on the preparation and integration of silicon-based ICs, optical filters and III/V semiconductors shall be discussed. Contents The general principle of µTP is based on the utilization of an elastomer stamp to transfer devices or arrays of devices from their native substrate (source) to a non-native target material [1]. A mandatory requirement for this transfer is that the stamp, typically made of polydimethylsiloxane (PDMS), provides tunable adhesion properties to the printable chiplet [2]. Thereby, high adhesion during the “pick-up” as well as low adhesion forces during the “placing” steps can be achieved.The general process flow for micro-transfer-printing is illustrated in Figure 1 .Therein, the main advantage of µTP, namely the extensive parallelization of the chip placement (schematics a.-e.), can be recognized. Such a parallelization offers the possibility of a major process time reduction.Prior to the transfer operation, the source wafer has to be prepared for the printing process. This involves the formation of reliable anchor and tether structures which carry the printable chiplets after the release etch. Another crucial requirement on these structures is that they provide a controlled micro-fracture and release the transfer chiplets to the stamp [3]. An example of a print-ready optical filter device is furthermore illustrated in Figure 1g.The target on the other hand has to be coated with an adhesion providing polymer (see red layer in Figure 1d.-f.) for which bisbenzocyclobutene (BCB) is applied at X-FAB.After the printing itself, a post-processing comprising the patterning of applied adhesion media, a wiring via a Cu redistribution layer (RDL) and a passivation is required to allow the functionality of active devices (see Figure 1f.). Figure 1h shows two 3D-integrated demonstrator devices which have been printed on a XL035 technology from X-FAB and which were afterwards connected via a Cu-RDL layer. Within the printing experiments of these chiplets a print yield of about 99.9% with a placement accuracy of down to 3σ ≤ 0.78µm has been achieved. Conclusions By this publication the Micro-transfer-printing (µTP) technology and its technical implementation will be introduced. To build up and develop µTP processes a pilot line has been installed in the X-FAB MEMS Foundry GmbH via a funded ECSEL project called “MICROPRINCE”. To execute the µTP technology for 3D integration several process steps have to be executed to prepare a source wafer for the printing operation, transfer the chiplets to a non-native target and connect them afterwards during the prost-processing. The process sequence itself will be explain in more detail within the presentation on examples of optical filters, silicon ASICs as well as III/V semiconductor chiplets. Acknowledgements This work is funded by ECSEL JU under grant agreement No 737465 and by the BMBF No ESECS16204. Further, the authors like to thank all X-FAB internal and external MICROPRINCE partners for their support.

With the advance of high-performance and small-size microelectromechanical systems (MEMS) devices, wafer-level packaging has gained increased attention over the past few years. Most MEMS packages must protect the often-fragile mechanical structures against the environment and provide the interface for the interaction with the next level in the packaging hierarchy. It is obvious that stable performance and high reliability are essential requirements of a packaged device. In this paper, a novel hermetic package, called the WL-¿P, recently developed for radio-frequency (RF)-filter and RF-duplexer, will be reviewed in terms of its construction, fabrication process, and electrical/mechanical performance. The package consists of a device wafer for a MEMS device and a cap wafer that has a micromachined cavity and through-wafer vias for electrical connections. The cap and device wafers are bonded to each other through a closed square loop of gold/tin eutectic solder at the peripheral edge. The via-in-cavity structure is designed in the cap substrate, with vertical via holes fabricated and fully electroplated with copper. The detailed design and fabrication technology of this new type of hermetically sealed package are presented with process flow. The performance evaluation and reliability results of a hermetic package will also be presented. The developed wafer-level hermetic package technology is able to fulfill today's requirements for hermetic and cost-effective packaging of high-speed RF-MEMS applications.

Wafer Level Chip Scale Package (WLCSP) technologies are being used more often in electronic components due to their smaller size and lower cost, and are being applied to larger die and ball matrix sizes. Originally implemented mainly in mobile devices (i.e., smartphones), WLCSP components are now frequently used in new product categories that have more stringent use conditions than the mobile space. The harsher use conditions raise a concern of solder joint reliability, especially in temperature cycling due to the difference in the coefficient of thermal expansion between the silicon die and the laminate motherboard. While cycle life can be extended by using underfill, underfilling makes the surface mount assembly process more complex and costly, increases cycle time and inhibits rework. To solve the challenge of extending cyclic life without underfill, new WLCSP structures and materials have been proposed. This paper describes the investigation of some of these innovative solutions through motherboard assembly and board level reliability testing. The package variables consisted of two WLCSP structures utilizing ball support mechanisms and a Bismuth (Bi) bearing solder ball that is expected to increase fatigue life. Packages were produced separately with each variable, along with legs that included both new packages and new alloy. The finished assemblies, along with a control leg of standard structure/solder, were subjected to drop testing and temperature cycling. Solder joint integrity was monitored in-situ to accurately identify duration to failure for Weibull analysis. The results clearly show that this new generation of WLCSP structures can offer dramatically improved fatigue life without a significant sacrifice in drop reliability. This benefit should allow the use of WLCSPs in more challenging environments, as well as providing designers the option of using larger package sizes in existing mobile designs.

The continued need for higher density designs with advanced electronic packaging technologies such as Ball Grid Array (BGA) and Chip Scale Packaging (CSP) and other commercial component technologies are important to Raytheon. Due to the costs associated with the development of certain high performance products, there is a critical need within Raytheon to develop rework capability of assemblies using these technologies. Unlike the commercial arena which produces high volume - low cost products such as cell-phones, personal digital assistants (PDA), computers and digital cameras, to name a few, the products developed by Raytheon Electronic Systems are considered low volume - high cost. The economics of the commercial arena indicate that reworking an electronic assembly is more the exception than the rule, whereas rework is a critical requirement for Raytheon. This paper will cover BGA/CSP rework, the process of repairing/modifying Printed Wiring Boards (PWB) when using these packages and the benefits associated with having this capability. In addition, we will highlight some of the lessons learned through our in–house process development. These capabilities stem from the leveraging of packaging technology development of the JPL/NASA led consortium, which Raytheon has been a member for the past seven years.

The important factors for packaging technology are IC packaging costs, the impact of the package on circuit and system performance, and the reliability of the package. Wafer level packaging technology is a promising solution for future IC generations. This paper reviews the wafer level bumping process and its requirement for thick resist coating and full field aligned exposure. 3D interconnect technology is a viable solution for increasing electronic device functional density and reducing total packaging costs. The critical issue is the ability to align and bond with precision, one micron or less, two silicon wafers or a silicon wafer to another substrate. For CMOS devices, this technology can be applied to chip-scale packaging and also to advanced 3D interconnect processes. In this paper, we describe a new approach to wafer-to-wafer alignment using alignment targets at the bond interface, i.e. face to face wafer alignment (SmartVieW/sup TM/) that relies on precision alignment positioning systems to register and align wafers with one micron or better precision.