Circuit placement in arbitrarily shaped regions using neural network

The second version of the simplified ART-based artificial neural network, named SARTNN2, is presented. The SARTNN2 model, which is made of an attentional and of an orienting subsystem, detects statistical regularities in a random sequence of multivalued input patterns. The SARTNN2 attentional subsystem consists of a flat, self-organizing Kohonen's artificial neural network which exploits a bubble competitive strategy. Both the attentional and the orienting subsystems exploit a new metric, named normalized vector distance (NVD), which provides a normalized measurement of the intervector distance between a multivalued vector pair. The NVD measurements, which are per cent values, feature adaptability to local statistics. SARTNN2 inherits the typical KANN plasticity in addition to the peculiar ART stability. Only two user-defined parameters, both having an intuitive physical meaning, are necessary for SARTNN2 to operate. The SARTNN2 model has been tested as a clustering algorithm in the unsupervised analysis of satellite imagery.

Circuit Partitioning generally formulated as graph partitioning problem is an important step in physical design of circuits. The use of Evolutionary techniques is increasingly used to solve NP complete problems i.e. Applications for logic minimization and simulation heuristics. This paper explores the evolutionary approach of genetic algorithm and propose a hybrid technique involving the strengths of the existing techniques resulting in a better partitioning and placement of circuits. It can further be extended to the Hardware/Software boundary of algorithms and can be applied to real world physical design problems.

Coupling Of Synthesis And Layout: Challenges And Solutions

The modeling and dynamical analysis of discrete chaotic systems is a vital research field, and various chaotic maps have been developed using mathematical and control-theoretic approaches. However, physical circuit design of mathematically defined discrete chaotic systems and the computation of their energy functions remain challenging and open problems. In this study, a two-dimensional (2D) chaotic map is constructed using an open-loop modulation coupling method, and its dynamical characteristics are analyzed using bifurcation diagrams. Lyapunov exponents (LEs) and spectral entropy (SE) complexity are also inspected under different parameter configurations. Furthermore, the proposed chaotic map is expressed using two distinct physical memristive circuits: one is composed of a magnetic flux-controlled memristor, a nonlinear resistor, and a capacitor; the other utilizes a charge-controlled memristor, a nonlinear resistor, and an inductor. Moreover, two energy functions are derived from the two memristor-coupled circuits for the proposed chaotic map. The results demonstrate that the mathematical model of the discrete chaotic system can be effectively expressed through these two nonlinear circuits. Our study offers a theoretical foundation and viable methodology for the physical circuit representation of discrete chaotic systems and determination of their energy functions.

Crack identification in magnetoelectroelastic materials using neural networks, self-organizing algorithms and boundary element method

Cell placement by self-organisation

Application of neural networks to detection of medical fraud

We examine the performance of several neural network vector quantization (VQ) methods on image coding. The VQ methods we look at are Kohonen's Self-Organizing Feature Map (KSOFM), Frequency-Sensitive Competitive Learning (FSCL), and Self-Creating and Organizing Neural Network (SCONN). We also look at variations of these algorithms by combining different methods. Our simulation results show that the best performance is achieved by the SCONN and the combination KSOFM and FSCL.

Contribution of the Physicochemical Properties of Active Pharmaceutical Ingredients to Tablet Properties Identified by Ensemble Artificial Neural Networks and Kohonen's Self-Organizing Maps

Having presented fabrication technology for IC chips in Chap. 2, we now investigate in detail an important aspect of the physical design process: data interfaces. We introduce circuit, layout and mask data structures, that is, the main input and output data in the design steps, in this chapter. First, we explain the input to physical design—circuit data—while focusing on schematics and netlists (Sect. 3.1); we then discuss the output of the physical design step: layout data such as layers and polygons (Sect. 3.2). Mask data, which are the data required by the foundry and generated at the end of the design process, are described in Sect. 3.3. Here, we introduce “layout post processing”, where amendments and additions to the chip layout data are performed in order to convert a physical layout into data for mask production. Technology data, provided by the chip manufacturing foundry, are crucial for producing the physical design. An important portion of these data are technological constraints which are modeled in the geometrical design rules used in physical design. Essentially, geometrical design rules are constraints for physical design, whose compliance ensures the manufacturability of the layout results. Geometrical design rules are presented in detail in Sect. 3.4. Technology data are organized in libraries. These libraries, which are extensively used in IC and PCB design, are covered in our final Sect. 3.5.

A new highly parallelizable method of moving mesh construction based on the Kohonen's Self-Organizing Maps (SOM) is proposed. This method belongs to a class of methods in which the mesh is an image under an appropriate mapping of a fixed mesh over a computational domain. Unlike the conventional methods of this class, the proposed method doesn't require solving complicated systems of nonlinear partial differential equations and is able to work with arbitrary time-dependent mesh density function. High efficiency of parallelization is conditioned by the inherent parallelism of the underlying stochastic SOM algorithm. Sequential as well as detailed parallel algorithms for moving mesh construction are proposed.

This paper presents a two-stage self-organizing map algorithm with threshold operation. Kohonen's basic SOM algorithm (BSOM) is simple and effective for data classification problems of high-dimensional data. But inactivated cells appear for specific input data and it causes to decline the ability of data classification. In order to solve this problem, BSOM with threshold operation (THSOM) was proposed recently. The THSOM algorithm, however, tends to loose topological structure of input data. Our two-stage self-organizing map algorithm inherits both good points of BSOM and THSOM. Numerical simulations reveal that the two-stage SOM can achieve small clustering error and high topology preservation in comparison with BSOM and THSOM.

Summary form only given. For many VLSI designs, validation has started to dominate the total design effort. In addition, historical trends are indicating that this problem will continue to grow. For example, data from Intel's lead microprocessor design efforts shows that the number of pre-silicon bugs has increased by a factor of four for every lead project for the last 25 years. If this trend is not broken, Intel's next lead design is likely to have to go through the find the bug, evaluate it, root cause it, it, and validate the fix process tens of thousands of times; potentially overwhelming the validation and design team. Thus one of the most critical goals for improving the design process is to break this bug trend. In the presentation, we introduce the integrated design and verification (IDV) system that has been developed at Intel for the last 5 years. IDV combines the design and validation efforts so that the task of design validation (i.e., Did we capture what we actually wanted?) is significantly simplified by means of a much smaller and much more stable high-level model. Furthermore, when the design is completed, so also is the implementation validation (i.e., Did we implement what we intended?). The latter is accomplished by linking the design process very tightly with the validation process. Although this idea is not new, the combination of correct-by-construction and correct-by-verification and the tight integration of a database of verified results is new and has led to a design environment that allows rapid design in which the validation problem has been significantly reduced. To make the presentation more realistic, we will use the design, from a high-level model to layout, of a floating point execution unit as a driving example. We discuss the early design phase in which the high-level model is refined using algorithmic transformations to a viable micro architecture; continue with the middle level design in which the actual logic implementation is derived and conclude with the final placement and layout stage. Although the design process conceptually is performed sequentially, we will illustrate the tight loop that IDV enables between physical design and logical/micro-architectural design. The latter is a critical component in enabling design convergence. In fact, in today's process technology, integration of physical and logical design is not optional but rather mandatory.

The Outlier detection is very active area of research in data mining where outlier is a mismatched data in dataset with respect to the other available data.In existing approaches the outlier detection done only on numeric dataset.For outlier detection if we use clustering method , then they mainly focus on those elements as outliers which are lying outside the clusters but it may possible that some of the unknown elements with any possible reasons became the part of the cluster so we have to concentrate on that also.The Proposed method uses hybrid approach to reduce the number of outliers.The number of outlier can only reduce by improving the cluster formulation method.The proposed method uses two data mining techniques for cluster formulation i.e. weighted k-means and neural network where weighted kmeans is the clustering technique that can apply on text and date data set as well as numeric data set.Weighted kmeans assign the weights to each element in dataset.The output of weighted k-means becomes the input for neural network where the neural network is the classification and clustering technique of data mining.Training is provided to the neural network and according to that neurons performed the testing.The neural network test the cluster formulated by weighted k-means to ensure that the clusters formulated by weighted k-means are group accordingly.There is lots of outlier detection methods present in data mining.The proposed method use Integrating Semantic Knowledge (SOF) for outlier detection.This method detects the semantic outlier where the semantic outlier is a data point that behaves differently with other data points in the same class or cluster.The main motive of this research work is to reduce the number of outliers by improving the cluster formulation methods so that outlier rate reduces and also to decrease the mean square error and improve the accuracy.The simulation result clearly shows that proposed method works pretty well as it significantly reduces the outlier.

Extending classical functional dependencies for physical database design