CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

For high-speed performance in computing and other applications which involve processing, computing, and analysis of any signal, digital CMOS circuits have been used mostly. Several pros over other families which include perfect logic levels, impeccable noise margins, better performance, and almost negligible static power dissipation CMOS logic family is preferred. As we need faster processing of signals, the demand of these circuits is high and is going to increase in near future. With integration, the number of transistors is increasing per chip area but the energy due to gate switching does not decrease with same rate. Hence power dissipation, reduction of heat is major concern in circuits. In this work, the positive feedback adiabatic logic PFAL-based design for digital circuits using CMOS is proposed and compared with the conventional circuit. The design is simulated, and with the comparison of conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit the proposed method has less power dissipation in terms of 80.871 pW while conventional CMOS circuit has 6.9090 nW with no change in behavior of the circuit. For full adder circuit conventional CMOS has 48.0452 pW while proposed PFAL-based full adder has 3.9089 pW.KeywordsAdiabaticLow power designPFAL designMultiplexerFull adderCMOS

CMOS chips are becoming increasingly important in computer circuitry. They have been widely used during the past decade, and they will continue to grow in popularity in those application areas that demand high performance. Challenging the prevailing opinion that circuit simulation can reveal all problems in CMOS circuits, Masakazu Shoji maintains that simulation cannot completely remove the often costly errors that occur in circuit design. To address the failure modes of these circuits more fully, he presents a new approach to CMOS circuit design based on his systematizing of circuit design error and his unique theory of CMOS digital circuit operation. In analyzing CMOS digital circuits, the author focuses not on effects originating from the characteristics of the device (MOSFET) but on those arising from their connection. This emphasis allows him to formulate a powerful but ultimately simple theory explaining the effects of connectivity by using a concept of the states of the circuits, called microstates. Shoji introduces microstate sequence diagrams that describe the state changes (or the circuit connectivity changes), and he uses his microstate theory to analyze many of the conventional CMOS digital circuits. These analyses are practically all in closed-form, and they provide easy physical interpretation of the circuit's working mechanisms, the parametric dependence of performance, and the circuit's failure modes. Originally published in 1992. The Princeton Legacy Library uses the latest print-on-demand technology to again make available previously out-of-print books from the distinguished backlist of Princeton University Press. These editions preserve the original texts of these important books while presenting them in durable paperback and hardcover editions. The goal of the Princeton Legacy Library is to vastly increase access to the rich scholarly heritage found in the thousands of books published by Princeton University Press since its founding in 1905.

In integrated circuits, clocking system consumes a colossal portion of chip power, which includes switching activities of flip-flops, latches, clock distribution networks. Power gating and clock gating are two of the most effective techniques that is applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits. Power gating is essentially for reducing leakage power by switching off power supply to the nonoperational power domain of the chip during certain mode of operation. Header and footer switches, isolation cells and State Retention Flip Flops (SRFFs) used for implementing power gating. Clock gating is for reducing dynamic power by controlling switching activities on the clock path. Generally, Gate, Latch, or FF based clock gating cells used for implementing clock gating. The combined use of the two solutions, however , possess some challenges in terms of practical integration of the required control logics and power/timing overhead associated to it. Here we present an analysis in Cadence virtuoso tool using 90nm technology using a simple PIPO (parallel in parallel out) shift register. This project specifically targets the combined application of clock and power gating techniques.

In order to guarantee proper junction of a system, a correct clock signal must be distributed. This paper proposes two methods for distributing the clock signal that take account of crosstalk noises generated on the clock signal line, which are applicable to conventional synchronous digital systems. For the clock signal of a pulse type, we propose a multiple clock pulse method that has the tolerance for an incorrect clock pulse induced by a crosstalk fault. For the clock signal of a level sensitive type, we propose a self-correction method for the change of the clock signal width during system operation. The circuits implemented by both methods can be inserted into clock signal lines as adapter circuits for the conventional clocked element and flip-flop, and as a result, the proposed methods are easily built in conventional synchronous digital circuits. We show effectiveness of our design by circuit simulation for the conventional flip-flop.

In the present scenario, designing a circuit with low power has become very important and challenging task, low power devices are the need of present electronics industries. In VLSI circuit design, power dissipation and leakage present are the critical design structures as they show anvital role in act of the battery. Power management of chip is the major challenge. Leakage power is a crucial parameter as the technology is shrinking (180 nanometer, 90 nanometer, 45 nanometer).The leakage current is increasing very fast so numerous technique has been proposed for leakage reduction in CMOS digital integrated circuit. This review paper demonstrates the various reduction showcase for CMOS integrated circuited.

Clock gating is one of the most popular techniques used in many synchronous circuits for reducing dynamic power dissipation and it is helpful for decreasing the ability of power wasted by digital circuits. The major power consuming in electronics product is the systems clock signal and it is responsible for transition state of the components and this typically leads to the switching power consumption. Several techniques are used to reduce power some of the developed techniques are power gating, clock gating, adiabatic logic etc,. In clock gating technique, the unwanted clock signal is deactivated or blocked and by this activity, low dynamic power consumption can be achieved. Summary of issues associated with above clock gating techniques are presented for the research community to enable them to take future research in the right direction.

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 /spl mu/m SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF.

It has been proposed that small amounts of energy dissipate when transfer through a rising Vdd. In typical power gate circuits, the PMOS transistors (P SW ) reduce the leakage of power by shutting off outer Vdd to the idle blocks. We expand this technique by utilizing active P SW , which are turned on and off by a clock signal. The proposed SCKVdd technique combines the power source gated mechanism and clock signal to generate stable progressive rising voltage to suppress peak and average currents effectively. The SCKVdd technique is a scalable, clock-controlled, self-stabilized voltage technique. This technique is easily implemented in generic digital circuits to reduce power dissipation. A normal CMOS circuit shows a dynamic power consumption increase proportional to the clock frequency. SCKVdd results in a lower-than-usual frequency dependency, and is suitable for high speed clock circuits. SCKVdd can be integrated with frequency, voltage scaling and an activated P SW number to implement an efficient power-performance trade-off mechanism. In experiments that investigated constant Vdd for MPEG VLD chips, power dissipation savings were in the range of 42% to 54% with only a small delay penalty.

In recent years, power dissipation in CMOS circuits has grown exponentially due to the fast technology scaling and the increase in complexity. Supply Voltage scaling is an effective technique to reduce dynamic power dissipation due to the non-linear relationship between dynamic power and Vdd. In other words, Vdd can be scaled freely except with limitation for below threshold voltage operation. The dynamic voltage scaling architecture mainly consists of dc-dc power regulator which is customised to produce variability on the Vdd. The implemented architecture can dynamically vary the Vdd from 300 mV to 1.2V, with initial setup time of 1.5 μsec. This paper investigates the effect of DVS on dynamic power dissipation in a Fast Fourier Transform multiplier core. Implementation of DVS on the multiplier blocks has shown 25% of average power reduction. The design was implemented using 0.12μm ST-Microelectronic 6-metal layer CMOS dual- process technology.KeywordsFast Fourier TransformPulse Width ModulatorCharge PumpFast Fourier Transform AlgorithmDynamic Voltage ScalingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

A resistance-inductance-capacitance (RLC) model is described for estimating current waveforms in digital CMOS circuits. The model is based on parameters that are readily derived from information available in board layout files and component data sheets or IBIS (I/O buffer information specification) files. Compared with the simpler triangular waveform traditionally used to approximate current in CMOS circuits, the RLC model more accurately estimates the shape of the current waveform in the time domain and the amplitudes of the upper harmonics in the frequency domain.

Current RFID systems rely on the RF transciever to transmit information and convert RF power to DC to operate any integrated digital circuits. Research investigating the application of RF signals directly on digital CMOS circuits without RF-DC conversion is an emerging area for RFID technologies. One crucial digital circuit for most RFID systems is memory, needed for storing operational instructions and sampled data. An in-depth study and comparison of subthreshold SRAM bitcells has been conducted to analyze how such memories will function in a subthreshold RF-only regime without the need for RF-DC conversion. Several SRAM cells were chosen for conversion into the RF-only family and measured against several metrics, including highest performance at lowest operating voltage, power consumption, and static noise margins (SNM). Including RF supply transistors, an 18-T subthreshold RF-only bitcell is proposed, capable of operating at a data rate of 100 kHz at VRF of 200mVRMS.

Due to fundamental physical limitations, conventional digital circuits have not been able to scale at the pace expected from Moore’s law. In addition, computationally intensive applications such as neural networks and computer vision demand large amounts of energy from digital circuits. As a result, energy efficient alternatives are needed in order to provide continued performance scaling. Analog circuits have many well known benefits: the ability to store more information onto a single wire and efficiently perform mathematical operations such as addition, subtraction, and differential equation solving. However, analog computing also comes with drawbacks such as its sensitivity to process variation and noise, limited scalability, programming difficulty, and poor compatibility with digital circuits and design tools. We propose to leverage the strengths of analog circuits and avoid its weaknesses by using digital circuits and time-encoded computation. Time-encoded circuits also operate on continuous data but are implemented using digital circuits. We propose a novel scalable general purpose analog processor using time-encoded circuits that is well suited for emerging applications that require high numeric precision. The processor’s datapath, including time-domain register file and function units are described. We evaluate our proposed approach using an implementation that is simulated with a 0.18µm TSMC process and demonstrate that this approach improves the performance of a scientific benchmark by 4x compared against conventional analog implementations and improves energy consumption by 146x compared against digital implementations.

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New complex and Low Power systems are being implemented using advanced Electronic Design Automation (EDA) tools. Low power designs are not only used in small size applications like mobile phones, tablets and handheld devices but also in high-performance computing applications. As the complexity increases day by day, the dissipation of power has emerged as one of the very important design constraints. In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. Flip-flops are critical timing elements in digital circuits which have a large impact on circuit speed and power consumption. The performance of the Flip-Flop is an important element to determine the performance of the synchronous circuit. In the research of low power and low voltage VLSI circuits, the use and implementation of Dual Edge Triggered Flip-Flop (DETFF) has gained more attention at the gate level design. The main advantage of using DETFF is that it allows one to maintain a constant throughput while operating at only half the clock frequency. In this paper, a dual-edge triggered sense amplifier flip-flop is designed for low power systems. For DETFF, the optimal delay, power consumption, and energy are determined as the primary figures of merit. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed.