Energy efficiency enhancement of sub-threshold digital CMOS

Current RFID systems rely on the RF transciever to transmit information and convert RF power to DC to operate any integrated digital circuits. Research investigating the application of RF signals directly on digital CMOS circuits without RF-DC conversion is an emerging area for RFID technologies. One crucial digital circuit for most RFID systems is memory, needed for storing operational instructions and sampled data. An in-depth study and comparison of subthreshold SRAM bitcells has been conducted to analyze how such memories will function in a subthreshold RF-only regime without the need for RF-DC conversion. Several SRAM cells were chosen for conversion into the RF-only family and measured against several metrics, including highest performance at lowest operating voltage, power consumption, and static noise margins (SNM). Including RF supply transistors, an 18-T subthreshold RF-only bitcell is proposed, capable of operating at a data rate of 100 kHz at VRF of 200mVRMS.

For high-speed performance in computing and other applications which involve processing, computing, and analysis of any signal, digital CMOS circuits have been used mostly. Several pros over other families which include perfect logic levels, impeccable noise margins, better performance, and almost negligible static power dissipation CMOS logic family is preferred. As we need faster processing of signals, the demand of these circuits is high and is going to increase in near future. With integration, the number of transistors is increasing per chip area but the energy due to gate switching does not decrease with same rate. Hence power dissipation, reduction of heat is major concern in circuits. In this work, the positive feedback adiabatic logic PFAL-based design for digital circuits using CMOS is proposed and compared with the conventional circuit. The design is simulated, and with the comparison of conventional CMOS 2:1 multiplexer circuit, the designed PFAL CMOS 2:1 multiplexer circuit the proposed method has less power dissipation in terms of 80.871 pW while conventional CMOS circuit has 6.9090 nW with no change in behavior of the circuit. For full adder circuit conventional CMOS has 48.0452 pW while proposed PFAL-based full adder has 3.9089 pW.KeywordsAdiabaticLow power designPFAL designMultiplexerFull adderCMOS

Memristors are considered as one promising candidate for future memory and computing fabrics. However, the design of memristor-based circuits is under a critical challenge of inevitable variations due to non-ideal fabrication processes and the resulted performance uncertainties. This kind of randomness can be utilized in many other applications, such as compressive sensing based data acquisition, which is conducted by a random sensing matrix. Existing compressive sensing systems are usually implemented in digital CMOS circuits, which suffer the problems of high hardware complexity and limited sampling speed. In this paper, we exploit the inherent variations in memristor devices to generate random sensing matrices for compressive sensing and achieve low cost and high performance operations. Simulation results demonstrate the advantages of the proposed memristor-based compressive sensing architecture.

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In integrated circuits, clocking system consumes a colossal portion of chip power, which includes switching activities of flip-flops, latches, clock distribution networks. Power gating and clock gating are two of the most effective techniques that is applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits. Power gating is essentially for reducing leakage power by switching off power supply to the nonoperational power domain of the chip during certain mode of operation. Header and footer switches, isolation cells and State Retention Flip Flops (SRFFs) used for implementing power gating. Clock gating is for reducing dynamic power by controlling switching activities on the clock path. Generally, Gate, Latch, or FF based clock gating cells used for implementing clock gating. The combined use of the two solutions, however , possess some challenges in terms of practical integration of the required control logics and power/timing overhead associated to it. Here we present an analysis in Cadence virtuoso tool using 90nm technology using a simple PIPO (parallel in parallel out) shift register. This project specifically targets the combined application of clock and power gating techniques.

CMOS circuits consume great dynamic power in switching. It has been proposed that energy transfer through a rising Vdd dissipates small amounts of energy. In typical power gate circuits, the high-performance PMOS transistors (PSW) that connect the circuit blocks to the power supply reduce leakage power by shutting off outer power (Vdd) to the idle blocks. We expand this technique by utilizing active PSW, which are turned on and off by clock signal. The PSW are fully turned on only for half of each clock cycle. This means that sufficient Vdd is provided to the circuit continuously for half of each clock cycle. In this manner, the circuit charge and discharge actions are cycle occur in different phases, and ramp Vdd is supplied to the designed circuit; we name this technique "CKVdd." CKVdd is a clock-controlled self-stabilized voltage technique, which generates stable ramp voltage to suppress the currents effectively. It is proposed to reduce dynamic power dissipation in conventional CMOS digital circuits. As compared to the conventional circuit, the circuits using CKVdd technique possesses several characteristics that differ from those of the current circuits using constant Vdd power source. First, CKVdd technique combines the power source and clock signal; it is an efficient low power technique. Second, CKVdd propose a feasible method to generate ramp-Vdd and low-Vdd. This technique would be convenient used to design generic low power digital circuits. Third, normal CMOS circuits show the dynamic power consumption increase proportional to the clock frequency. CKVdd results in a lower-than-usual frequency dependency, it is suitable used to design high clock speed circuits. In investigating constant Vdd for MPEG VLD decoders, CKVdd-circuit reduces 48% of the usual power dissipation and 88% of the usual peak current with small delay penalty.

This paper reports the evolution of the bootstrap techniques in low-voltage CMOS digital VLSI circuits in the past. Combining bootstrap and DTMOS techniques, low-voltage CMOS digital VLSI circuits using a very low power supply voltage such as 0.5V have been developed for low-power SOC applications.

In sequential circuits, the current output can depend on both past and current inputs. However, certain kinds of sequential circuits do not refer to all of the past inputs to generate the current output; but only to a subset of past inputs. This paper investigates which subset of past inputs a sequential circuit refers to, and proposes a new classification of sequential circuits based on this criterion. While the conventional classification of sequential circuits distinguishes between synchronous and asynchronous circuits, the new classification consolidates synchronous circuits and multiple clock domain circuits into the same category. This is consistent with the notion that “multiple clock domain circuits are analogous to synchronous circuits,” and thus, the proposed classification appears valid from this perspective. It is expected that a method underlying our classification will allow a deeper understanding of sequential circuits.

Reliability of a focused ion beam repair on digital cmos circuits

Digital circuits operating in the sub-threshold regime are able to perform minimum energy operation at a given delay. In the sub-threshold regime circuit delay, hence the leakage energy consumption depends on the supply voltage exponentially. By reducing the idle time of the circuit both the supply voltage that realizes minimum energy operation and the energy consumption can be reduced. This paper presents an in-depth comparison of synchronous and asynchronous techniques in the sub-threshold operating regime for their energy efficiency. First, transistor level accurate high level sub-threshold energy consumption model is developed for both techniques. Afterwards, using the model, energy consumption reduction due to the asynchronous operation is investigated analytically. Different architectural improvements such as pipelining and parallelism are considered. The model has also been applied to the benchmark circuits for comparing real world energy consumption values. From our analysis and simulations we have found out that asynchronous operation in the sub- threshold regime significantly lowers the supply voltage value that realizes the minimum energy operation and operating the digital circuits at a lower supply voltage value result in lower energy operation. Asynchronous operation resulted in energy consumption savings of up to 51% on the ISCAS85 benchmark circuits synthesized in a digital CMOS 0.18 m process.

SUMMARY This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in the subthreshold region with no extra energy cost. The optimum pMOS-to-nMOS width ratio is obtained and compared through three approaches: 1) finding the maximum current-over-capacitance ratio of a biased transistor; 2) deriving an analytical expression by minimizing the delay of an inverter; and 3) simulating different CMOS logic gates in the subthreshold region. Simulation results illustrate that in the subthreshold region, the frequency attains its maximum at the optimum pMOS-to-nMOS width ratio independent of the supply voltage. Using this optimum value in designing a carry-look-ahead adder improves the propagation delay, energy consumption, and energy-delay product by up to 33%, 36%, and 57%, receptively, compared with when the conventional pMOS-to-nMOS width ratio (in the superthreshold region) is used. We verified our analytical model by performing circuit simulations in four CMOS technologies (TSMC 180 nm, IBM 130 nm, TSMC 90 nm, and ST 65 nm).

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.