Evolution of bootstrap techniques in low-voltage CMOS digital VLSI circuits for SOC applications

As feature sizes of integrated circuits continue to shrink and demand for low power operation continues to increase, power supply voltages may eventually be reduced to the level where noise becomes significant compared with signals. This would cause digital logic circuits to exhibit non-deterministic behavior. In this paper, we study the stochastic behavior of simple digital circuits operating at low power supply voltages. We develop a method for modelling the stochastic behavior of circuits and apply the method to a CMOS inverter. We use numerical simulations of stochastic differential equations to obtain time- domain transient analysis of the CMOS inverter and magnitude statistics from multiple sample paths. Further, we derive the output distribution at steady state from first principles. We characterize the switching error and the information transmission based on the output steady state distribution. This study provides a detailed understanding of how noise affects the operation of the CMOS inverter at low power supply voltages. The method we develop here can also be extended to other circuits where stochastic sample paths and sample statistics are necessary to characterize the circuits. Traditional frequency domain noise analysis is not adequate to provide this information.

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VLV</sub> are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

Transition metal dichalcogenides (TMDC) have remarkable properties for the next generation of electronic devices [1]. A complementary metal-oxide-semiconductor (CMOS) inverter consisting of pairs of p-type and n-type field-effect transistor (FET) is a fundamental building block in modern digital electronics [2]. Therefore, realization of both p-type and n-type FETs based on semiconducting TMDC is of particular importance. Among various semiconducting TMDC, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [3]. These prominent features of WSe2 motivates the fabrication and characterization of a CMOS inverter. One of the significant challenges is to develop a high-gain CMOS inverter for operation at a low power supply voltage (Vdd) for future low power digital electronics. Previous studies on a WSe2 CMOS inverter were limited to operation with a low gain of 3 or a high Vdd of more than 1 V under conditions of relatively low gate capacitance and degraded interfacial properties [3-5]. This study addressed these issues by developing a doping technique and gate stack technology to demonstrate the high-gain with low-Vdd operation of a WSe2 CMOS inverter [6]. The focus is on the doping technique of both electrons and holes to a WSe2 layer by simple spin-coating. Of particular interest in this study is the impact of gate stack technology on the CMOS inverter characteristics in low-Vdd operation. In this study, a hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is applied to a WSe2 CMOS inverter for high-gain low-Vdd operation since superior interfacial properties with high gate capacitance have been reported in molybdenum disulfide (MoS2) FETs.For p-type WSe2 FETs, the fluoropolymer CYTOP (AGC, CTX-809A) was applied since polarization in CYTOP due to the difference in electronegativity between C–F bonds generates holes in WSe2. On the other hand, poly(vinyl alcohol) (PVA) was utilized for n-type WSe2 FETs because positive charges in PVA accumulates electrons in WSe2. The resin solutions of both CYTOP and PVA were purchased from a commercial supplier. A heavily doped p-type silicon substrate (p+-Si) was thermally oxidized to form a 60 nm thick silicon dioxide (SiO2) layer for the global back-gate architecture. Palladium (Pd) and gold (Au) as the source and drain contacts for p-type and n-type WSe2 FETs were fabricated by the lift-off process, respectively. An aluminum (Al) gate was prepared and a hybrid SAM/AlOx gate dielectric was formed by oxygen (O2) plasma and an immersion process. After that, mechanically exfoliated WSe2 was transferred with a poly(dimethylsiloxane) (PDMS) stamp. Finally, CYTOP and PVA were deposited by spin-coating for p-type and n-type WSe2 FETs, respectively.Figures 1 (a) and (b) show the Id–Vg characteristics of fabricated FETs. For the p-type WSe2 FET, a small SS of 78 mV/dec and an on/off ratio of about 106 order were observed. On the other hand, the Id–Vg characteristics of the n-type WSe2 FET were degraded compared with those of the p-type WSe2 FET because of the Schottky contacts.Figures 2 (a) and (b) show the transfer characteristics and gain as a function of Vdd in CMOS inverter. The gain of the CMOS inverter increased to as high as 9 at Vdd of 0.5 V.Figure 3 shows the benchmark of this study. Our proposed concepts enabled the operation with high gain at a low Vdd as low as 0.5 V for the WSe2 CMOS inverter, which had not been realized in previous studies. The dangling-bond-free and ultrathin SAM/AlOx gate dielectric has an important role in the low-Vdd operation of the WSe2 CMOS inverter. This study opens up interesting directions for the research and development of TMDC-based devices and circuits.

This paper presents a new study over logics circuit operation in subthreshold and threshold region. CMOS circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate for high frequency and with low voltage source. A FFT processor is the most critical part on speed in multi-carrier orthogonal frequency division multiplexing (OFDM) communication systems. In these systems, power dissipation is usually one of the major concerns. In this report, we evaluate the low-power consumption of a radix-2 pipeline FFT and concurrent FFT with low voltage power supply. FFT simulation results clearly show that low voltage is not a barrier for logic design to operate at high frequency.

A vision chip based on pulse frequency modulation (PFM) is proposed as a retinal prosthesis device for use in subretinal implantation. A pixel circuit of PFM has been fabricated using standard CMOS technology. A dynamic range of 40 dB is demonstrated at a low power supply voltage of 1 V. It is found that the competition between the charge current to the photodiode and the photocurrent affects the output pulse characteristics under the conditionds of low power supply voltage and strong light illumination. For in vitro and in vivo experiments, two methods of improving the PFM circuits are considered. One is controlling the pulse frequency. By adding one transistor to the PFM circuit, the output pulse frequency can be experimentally controlled by a factor of two. The other is using a biphasic output, which is required to keep a charge balance in a living body. By introducing differential circuits, the biphasic output has been confirmed by simulation.

One of the major problems faced by the designer when operating CMOS static logic circuits at low power supply voltages (normalized to V/sub T/) is that the delay spread introduced by today's IC manufacturing variations can increase dramatically. In this paper we describe an approach for decreasing the delay spread and power spread in ICs based on adaptively servoing the circuits between static CMOS operation and QuadRail operation. An on-chip series-regulator employing a dummy delay path is used to generate the adaptive low swing power supply rails making this approach fully compatible with a standard CMOS IC design methodology. Simulation results are presented demonstrating that for a 16*16+36-bit multiplier-accumulator designed in 0.5 /spl mu/m CMOS process the proposed approach decreases the delay spread from 3.9/spl times/ to 2.3/spl times/ and the power spread from 3.6/spl times/ to 1.8/spl times/.

The results of measurements of the transient thermal characteristics (TTC) of CMOS digital integrated circuits (DIC) for using the voltage out low and voltage out high as temperature-sensitive parameters (TSP) are presented. Options for improving the accuracy of measuring the CMOS TTC DIC at a low supply voltage are considered.

Sense Amplifier is one of the major circuits in CMOS nonvolatile memories. The aim of this research is to implement Sense Amplifier in 0.18µm CMOS process to achieve both the lower reading power and superior reliability for sensing operation. In RFID transponder, EEPROM are used to store data. Memory access time, power dissipation and the reliability of an EEPROM is vigorously influenced by the features of the SA. Current type SA experience the larger current or power dissipation problems, which is not suitable for low voltage applications of RFID transponder. The proposed voltage-type SA is able to execute under a very low power supply voltage (VDD) between 1V to 2.6V VDD. The SA circuit implemented within the temperature range from -25 0 C to 125 0 C. The compact layout design has been carried out to evaluate the efficiency of the circuit. The modified low voltage-type SA is appropriate for low-voltage applications like RFID EEPROM. Ill. 6, bibl. 10, tabl. 1 (in English; abstracts in English and Lithuanian). DOI: http://dx.doi.org/10.5755/j01.eee.120.4.1466

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 /spl mu/A are drawn by the AAC circuit.

Nowadays IC designers are constantly challenged not only with single-chip integration but also with low-voltage and low-power designs. This is motivated both by the increasing demand of low-voltage low-power IC designs from most market segments and by the reliability concern under voltage scaling of deep-submicron CMOS processes. While many low-voltage RF circuits [SHA 97, WAN 98, WON 02] have been able to operate at very low supply voltages, and recently low-voltage receiver front-end [UGA 01] has been demonstrated with special SIMOX/CMOS processes of low VT, the possibility of integrating 1-V channel-select filter and A/D converter in a CMOS process with high-VT is still unknown.

Multi-band RF front-ends with adaptive image rejection : a DECT/Bluetooth study case

A new design methodology of high performance CMOS MPU that applies ultra-low VTH, which is necessary to improve circuit performance with low power supply voltage, is discussed. The multi-V/sub TH/, the IDDQ measurement with back bias control at low temperature and IDDQ technologies are applied in order to speed up, without increasing background leakage, IDDQ test. As a result, operation frequency of 64 bit MPU was successfully improved 340 MHz to 560 MHz without lowering IDDQ quality.

In this study, two new grounded metal oxide semiconductor field effect transistor (MOSFET)-C active inductors (AIs) are proposed. The proposed AIs contain only eight MOS transistors and a single grounded capacitor that is attractive for integrated circuit fabrication. Inductance values of them can be electronically tuned by a single control voltage. They do not include any current sources. Therefore, the designs of the proposed AIs are simple and useful. They do not suffer from body effects. Hence, they can be designed with low power supply voltages. Simulation results by using the Cadence analog environment program with 180 nm Taiwan Semiconductor Manufacturing Company (TSMC) nm technology parameters are carried out to indicate the performance of them. Layouts of both proposed AIs occupy the same area of about 78 μm × 78 μm. Postlayout simulation results are given to confirm the validity of the theoretical analysis.

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS - VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.