A memristor-based compressive sensing architecture

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

Memristors are considered as one promising device for implementing future memory and computing systems. However, design of memristor-based circuits faces a key challenge to deal with variations from nonideal fabrication processes and the resulting performance uncertainties. Fortunately, this randomness can be exploited in many other applications, such as compressive sensing-based data acquisition, which relies on a random sensing matrix in digital or analog formats. Existing compressive sensing systems are usually implemented in digital CMOS circuits, which introduce high hardware complexity and limited sampling speed. In this paper, we studied the process variations in memristor devices and developed an analytical model to evaluate the properties of analog random sensing matrices for compressive sensing applications. Simulations are carried out to demonstrate the statistical distributions of memristor arrays under different filament lengths and identify the optimal switching strategy. The proposed memristor-based compressive sensing circuit also has the advantages of low complexity and high performance. A case study is conducted for compressive image acquisition using the proposed approach.

Non-volatile memories (NVM) including flash memories and resistive memories have attracted significant interest as data storage media. Flash memories are widely employed in mobile devices and solid-state drives (SSD). Resistive memories are promising as storage class memory and embedded memory applications. Data reliability is the fundamental requirement of NVM as data storage media. However, modern nano-scale NVM suffers from challenges of inter-cell interference (ICI), charge leakage, and write endurance, which threaten the reliability of stored data. In order to cope with these adverse effects, advanced coding techniques including soft decision decoding have been investigated actively. However, current coding techniques do not capture the physical properties of NVM well, so the improvement of data reliability is limited. Although soft decision decoding improves the data reliability by using soft decision values, it degrades read speed performance due to multiple read operations needed to obtain soft decision values. In this dissertation, we explore coding schemes that use side information corresponding to the physical phenomena to improve the data reliability significantly. The side information is obtained before writing data into memory and incorporated during the encoding stage. Hence, the proposed coding schemes maintain the read speed whereas the write speed performance would be degraded. It is a big advantage from the perspective of speed performance since the read speed is more critical than the write speed in many memory applications. First, this dissertation investigates the coding techniques for memory with stuckat defects. The idea of coding techniques for memory with stuck-at defects is employed to handle critical problems of flash memories and resistive memories. For 2D planar flash memories, we propose a coding scheme that combats the ICI, which is a primary challenge of 2D planar flash memories. Also, we propose a coding scheme that reduces the effect of fast detrapping, a degradation factor in 3D vertical flash memories. Finally, we investigate the coding techniques that improve write endurance and power consumption of resistive memories.

In today's society, we are flooded with massive volumes of data in the order of a billion gigabytes on a daily basis from pervasive sensors. It is becoming increasingly challenging to locally store and transport the acquired data to a central location for signal/data processing (i.e., for inference). To alleviate these problems, it is evident that there is an urgent need to significantly reduce the sensing cost (i.e., the number of expensive sensors) as well as the related memory and bandwidth requirements by developing unconventional sensing mechanisms to extract as much information as possible yet collecting fewer data. The first aim of this thesis is to develop theory and algorithms for data reduction. We develop a data reduction tool called sparse sensing, which consists of a deterministic and structured sensing function (guided by a sparse vector) that is optimally designed to achieve a desired inference performance with the reduced number of data samples. The first part of this thesis is dedicated to the development of sparse sensing mechanisms and convex programs to efficiently design sparse sensing functions. We design sparse sensing functions under the assumption that the data is not yet available and the model information is perfectly known. Sparse sensing offers a number of advantages over compressed sensing (a state-of-the-art data reduction method for sparse signal recovery). One of the major differences is that in sparse sensing the underlying signals need not be sparse. This allows us to consider general signal processing tasks (not just sparse signal recovery) under the proposed sparse sensing framework. Specifically, we focus on fundamental statistical inference tasks, like estimation, filtering, and detection. In essence, we present topics that transform classical (e.g., random or uniform) sensing methods to low-cost data acquisition mechanisms tailored for specific inference tasks. The developed framework can be applied to sensor selection, sensor placement, or sensor scheduling, for example. In the second part of this thesis, we focus on some applications related to distributed sampling using sensor networks. Sensor networks can be used as a spatial sampling device, that is, to faithfully represent distributed signals (e.g., a spatially varying phenomenon such as a temperature field). On top of that, the distributed signals can exist in space and time, where the temporal sampling is achieved using analog-to-digital converters, for example. Each sensor has an independent sample clock, and its stability essentially determines the alignment of the temporal sampling grid across the sensors. Due to imperfections in the oscillator, the sample clocks drift from each other, resulting in the misalignment of the temporal sampling grids. To overcome this issue, we devise a mechanism to distribute the sample clock wirelessly. Specifically, we perform wireless clock synchronization based on the time-of-flight measurements of broadcast messages. In addition, clock synchronization also plays a central role in other time-based sensor network applications such as localization. Localization is increasingly gaining popularity in many applications, especially for monitoring environments beyond human reach, e.g., using robots or drones with several sensor units mounted on it. Consequently we now have to localize more than one sensor or even localize the whole sensing platform. Therefore, we extend the classical localization paradigm to localize a (rigid) sensing platform by exploiting the knowledge of the sensor placement on the platform. In particular, we develop algorithms for rigid body localization, i.e., for estimating the position and orientation of the rigid platform using distance measurements. Given the central role of sensing and sensor networks, the results presented in this thesis impacts a wide range of applications.

We report on a room temperature Aerosol Jet printed two-terminal WSe2 crossbar architecture device on flexible substrate that achieves dual functionality of both a resistive random access memory (ReRAM), as well as a photosensor. As a ReRAM, the silver contacted WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> device exhibits forming free, sub 1-V switching voltage, and an on-off ratio of 2 orders. Furthermore, the WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ReRAM exhibits both volatile and non-volatile switching behavior with a transition set current of 2 μA, translating to a low operating power of 16 μW. As a photosensor with the same architecture, the transparent CNT electrodes contacted device allows incident light to pass through for photocurrent generation. The two terminals device allows photo sensitivity to be tuned by bias application. In such mode, a maximum photo responsivity of 1 A/W at a visible light wavelength of 660 nm is exhibited by the device at a bias of 1 V, allowing weak light signals to be amplified. In both cases, the WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> device retains its functionality even after bending down to a radius of 5 cm. The fabrication process can be up-scaled and has great potential to be used for conformal electronics system integration.

Field programmable memory BIST controllers are becoming a necessity to target manufacturing defects in embedded memories. For 65nm and below, random defects are not the only ones affecting the yield of a process. Systematic as well as parametric defects are now the predominant causes of memory failures and have to be addressed. Conventional memory BIST algorithms are usually targeted to catch random defects. In order to catch such systematic and parametric defects, it is necessary to have the flexibility to apply new algorithms to embedded memories after manufacturing. In this paper, a field programmable memory BIST architecture is proposed to support multiple loops within a test step of an algorithm, including nested loops. These controllers, therefore, guarantee supporting complex algorithm necessary to target defects during failure analysis that could help yield ramp up or reduce test escapes. In addition, the proposed architecture is modular in nature and allows optimizing the complexity of the controller along with area and performance

In the last forty years the semiconductor industry focused on the downscaling process of the CMOS (Complementary Metal-Oxide-Semiconductor) technology, trying to follow as much as possible the empirical Moore's Law. In the last five years this trend has been facing technology limits that have led to the development of a new research field, named Beyond CMOS, which investigates new electron devices concept and materials that can replace or co-integrate the standard technology, to make large scale integrated (LSI), high performance, low power devices. Carbon nanotubes (CNTs) are considered one of the most promising materials for Beyond CMOS devices, both at front-end and back-end level. The development of the research on this new organic material is due to its nanometer scale dimensions and to its outstanding electrical (metallic and semiconducting behavior, ballistic conduction, current density > 109 A/cm2) and mechanical (Young's modulus ∼1 TPa) properties, nevertheless due to its low mass (mass density ρ = 1300 kg/m3). Among the several CNT applications already reported in literature (interconnections, sensors, transistors, memory, etc.), a particular interest is on their use to build Nano-Electro-Mechanical (NEM) devices, such as resonators and switches. NEM relays based on carbon nanotubes show large-current density drive and high speed operation compared to metal-based NEMS counterparts, low actuation voltage and low power, performances which are promising for radio-frequency (RF) applications, where RF MEM devices are considered as replacement solution for their off-chip and/or solid-state counterparts in front-end transceivers. Most of the previously reported CNT NEM switches concerns relay configuration based on one single movable nanotube and its DC characterization. Despite individual proof-of-concept merits, an electromechanical switch based on a single CNT usually presents an output signal level that is too low for practical applications and a poor reliable fabrication process, which opposes the precise control at wafer level achieved by standard technology. Alternatively, a very large-scale integration of NEM devices requires the exploitation of high-density aligned arrays of nanotubes, grown in precise locations and that could be patterned into well-defined and controlled configurations. The objective of this research work was to develop LSI NEM switches based on high dense carbon nanotube arrays in the back end of the line (BEOL), with conductive and capacitive contacts and tested from DC up to high frequency (RF), in order to evaluate their performances in a wide range of operations. The synthesis process of carbon nanotubes was performed by thermal CVD and temperature, gas concentration and catalyst pretreatment were optimized to achieve high dense aligned CNT arrays. A study on the catalyst geometries and on the substrate materials were performed in order to obtain horizontal aligned arrays grown directly on metallic substrate without density change. We developed a novel surface micromachining process to suspend CNT arrays. The DC characterization of CNT NEM switches was exploited to extract the equivalent electromechanical properties of the CNT membranes, since they behave as a new body material. We extracted an equivalent flexural modulus of 8.5 GPa and a resistivity of 0.0077 Ωcm. The devices, in both configurations, present a very low actuation voltage, below 10 V, lower than typical metal NEM switch for the same dimensions and a comparable switching time. The RF characterization was performed in the telecommunication frequency range (up to 6 GHz) showing reasonably high isolation and low insertion loss. The relay shows a lower reliability than the capacitive switch, due to the elevated drive current which induces the CNTs burning at the metal-to-metal interface. The RF measurements were used to extract the parameters of the proposed devices equivalent lumped model. Several implementations of CNT NEM switches, both for DC (reconfigurable interconnects, logic functions, memories) and RF (signal routing purposes in RF system Front-Ends, phase shifting networks or digitalized capacitor banks) applications, were reported.

Since the birth of charge coupled devices (CCD) and the complementary metal-oxide-semiconductor (CMOS) active pixel sensors, pixel pitch of digital image sensors has been continuously shrinking to meet the resolution and size requirements of the cameras. However, shrinking pixels reduces the maximum number of photons a sensor can hold, a phenomenon broadly known as the full-well capacity limit. The drop in full-well capacity causes drop in signal-to-noise ratio and dynamic range.The Quanta Image Sensor (QIS) is a class of solid-state image sensors proposed by Eric Fossum in 2005 as a potential solution for the limited full-well capacity problem. QIS is envisioned to be the next generation image sensor after CCD and CMOS since it enables sub-diffraction-limit pixels without the inherited problems of pixel shrinking. Equipped with a massive number of detectors that have single-photon sensitivity, the sensor counts the incoming photons and triggers a binary response “1” if the photon count exceeds a threshold, or “0” otherwise. To acquire an image, the sensor oversamples the space and time to generate a sequence of binary bit maps. Because of this binary sensing mechanism, the full-well capacity, signal-to-noise ratio and the dynamic range can all be improved using an appropriate image reconstruction algorithm. The contribution of this thesis is to address three image processing problems in QIS: 1) Image reconstruction, 2) Threshold design and 3) Color filter array design.Part 1 of the thesis focuses on reconstructing the latent grayscale image from the QIS binary measurements. Image reconstruction is a necessary step for QIS because the raw binary measurements are not images. Previous methods in the literature use iterative algorithms which are computationally expensive. By modeling the QIS binary measurements as quantized Poisson random variables, a new non-iterative image reconstruction method based on the Transform-Denoise framework is proposed. Experimental results show that the new method produces better quality images while requiring less computing time.Part 2 of the thesis considers the threshold design problem of a QIS. A spatially-varying threshold can significantly improve the reconstruction quality and the dynamic range. However, no known method of how to achieve this can be found in the literature. The theoretical analysis of this part shows that the optimal threshold should match with the underlying pixel intensity. In addition, the analysis proves the existence of a set of thresholds around the optimal threshold that give asymptotically unbiased reconstructions. The asymptotic unbiasedness has a phase transition behavior. A new threshold update scheme based on this idea is proposed. Experimentally, the new method can provide good estimates of the thresholds with less computing budget compared to existing methods.Part 3 of the thesis extends QIS capabilities to color imaging by studying how a color filter array should be designed. Because of the small pixel pitch of QIS, crosstalk between neighboring pixels is inevitable and should be considered when designing the color filter arrays. However, optimizing the light efficiency while suppressing aliasing and crosstalk in a color filter array are conflicting tasks. A new optimization framework is proposed to solve the problem. The new framework unifies several mainstream design criteria while offering generality and flexibility. Extensive experimental comparisons demonstrate the effectiveness of the framework.

Objective To explore the effect of continuous care family visiting on disease uncertainty and psychological conditions in non-dialysis chronic renal failure patients. Methods Totals of 120 non-dialysis chronic renal failure patients admitted to our department from July 2011 to June 2013 were selected. In accordance with the principle of randomized controlling, patients were divided into observation group and control group, with 60 cases in each. The control group received conventional family supervision, while the observation group underwent continuous care family visiting in addition to traditional family supervision. The illness uncertainty and psychological conditions of two groups were assessed and compared before and after the intervention. Results Before the intervention, disease uncertainty and psychological conditions of the two groups were not significantly different (P>0.05). After the intervention, the scores of sense of uncertainty, complexity, unpredictability, lack of disease-related information or inconformity were (35.3±5.1), (8.7±3.0), (8.8±3.5) and (12.5±2.8), which were significantly better than those in the control group (t=11.70, 11.10, 10.70, 8.21, respectively; P 0.05). After the intervention, the scores of anxiety and depression were (42.1±5.8) and (41.3±5.6) in the observation group, which were significantly lower than those in the control group (t=3.440, 5.740, respectively; P<0.05). Conclusions Continuous care family visiting cannot only significantly alleviate the uncertainty of illness in non-dialysis chronic renal failure patients, but also improve their mental condition and quality of life, and enhance their motivation and adherence to treatment. Key words: Chronic renal failure; Anxiety; Depression; Continuous care family visiting

The use of nanowire crossbars to build devices with large storage capabilities is a very promising architectural paradigm for forthcoming nanoscale memory devices. However, this new type of memory devices raises questions regarding how to test their correct operation. In particular, the variability affecting the decoder is expected to make very complex the test of these new devices. In this paper we present a method to simplify the test of these new devices by using a current thresholder to detect badly addressed nanowires. In the proposed method, the thresholder design is based on a stochastic and perturbative model of the current through the nanowires. Thus, the calculated thresholder parameters are robust against technology variation. As our experimental results indicate, the thresholder error probability is initially only ~ 10-4, which can be also reduced further (up to ~ 60×) by trading-off only ~ 35% area overhead in the memory.

Parallel turbo decoder architectures have recently been proposed to reach high-throughput channel decoding capacity. However, the implementation of the underlying parallel interleaving subsystem suffers from memory access conflicts; those translate into logic overhead and critical path issues which are blocking factors for handheld system-on-chip solutions. In this paper, we explore several architecture and VLSI design strategies that drastically reduce the logic overhead and data-path delays of concurrent interleaving architectures. A stalling mechanism is introduced that reduces the interleaving subsystem die area and improves the architecture scalability with respect to the number of MAP producers. ASIC synthesis results in 0.18/spl mu/m and 0.13/spl mu/m CMOS STMicroelectronics technologies demonstrate the efficiency of the proposed VLSI concurrent interleaving architecture.

An all digital architecture was presented to realize the logarithm modeled automatic gain control(AGC) loop based on field programmable gates array(FPGA) platform.The architecture is mainly made up of four modules,including envelope detector,coordinator rotation digital computer(CORDIC) based iterative realization of effective hyperbolic function,infinite impulse response(IIR) based loop filter,and reconfigurable control logic generator.Envelope detector can meet the filter performance requirement only with finite impulse response(FIR) filter of low order.Symmetric coefficient based transposed architecture reduces the number of multipliers in filter to the half.By approximation to analog integrator and suitable process,IIR based filter can simplify the architecture of digital integrator.The logarithm convertor is easy to be realized by CORDIC based iterative hyperbolic function processor.The architecture can also output with random precision,and realize the compromise of circuit resources and speed,which overcomes the high demand for random access memory(RAM) in traditional algorithms.With fully parallel pipeline architecture,the maximum working clock can achieve 206 MHz.Finally,the realization results based on the FPGA processor and the hardware simulation were given.Experimental results were consistent well with the theoretical analysis.

Rapid advances in information processing, communication and sensing technologies have enabled more and more devices to be provided with embedded processors, networking capabilities and sensors. For the field of estimation and control, it is now possible to consider an architecture in which many simple components communicate and cooperate to achieve a joint team goal. This distributed (or networked) architecture promises much in terms of performance, reliability and simplicity of design; however, at the same time, it requires extending the traditional theories of control, communication and computation and, in fact, looking at a unified picture of the three fields. A systematic theory of how to design distributed systems is currently lacking. This dissertation takes the first steps towards understanding the effects of imperfect information flow in distributed systems from an estimation and control perspective and coming up with new design principles to counter these effects. Designing networked systems is difficult because such systems challenge two basic assumptions of traditional control theory - presence of a central node with access to all the information about the system and perfect transmission of information among components. We formulate and solve many problems that deal with the removal of one, or both, of these assumptions. The chief idea explored in this dissertation is the joint design of information flow and the control law. While traditional control design has concentrated on calculating the optimal control input by assuming a particular information flow between the components, our approach seeks to synthesize the optimal information flow along with the optimal control law that satisfies the constraints of the information flow. Thus besides the question of 'What should an agent do?', the questions of 'Whom should an agent talk to?', 'What should an agent communicate?', 'When should an agent communicate?' and so on also have to be answered. The design of the information flow represents an important degree of freedom available to the system designer that has hitherto largely been ignored. As we demonstrate in the dissertation, the joint design of information flow and the optimal control input satisfying the constraints of that information flow yields large improvements in performance over simply trying to fit traditional design theories on distributed systems. We begin by formulating a distributed control problem in which many agents in a formation need to cooperate to minimize a joint cost function. We provide numerical algorithms to synthesize the optimal constrained control law that involve solving linear equations only and hence are free from numerical issues plaguing the other approaches proposed in the literature. We then provide and analyze a model to understand the issue of designing the topology according to which the agents interact. The results are very surprising since there are cases when allowing communication to happen between two agents may, in fact, be detrimental to the performance. We then move on to consider the effects of communication channels on control performance. To counter such effects, we propose the idea of encoding information for the purpose of estimation and control prior to transmission. Although information theoretic techniques are not possible in our problem, we are able to solve for a recursive yet optimal encoder / decoder structure in many cases. This information flow design oriented approach has unique advantages such as being optimal for any packet drop pattern, being able to include the effect of known but random delays easily, letting us escape the limits set by reliability for transmission of data across a network by using intermediate nodes as 'repeaters' similar to a digital communication network and so on. We finally take a look at combining the effects of multiple sources of information and communication channels on estimation and control. We look at a distributed estimation problem in which, at every time step, only a subset out of many sensors can transmit information to the estimator. This is also a representative resource allocation problem. We propose the idea of stochastic communication patterns that allows us to include the effects of communication channels explicitly during system design. Thus, instead of tree-search based algorithms proposed in the literature, we provide stochastic scheduling algorithms that can take into account the random packet drop effect of the channels. We also consider a distributed control problem with switching topologies and solve for the optimal controller. The tools that we develop are applicable to many other scenarios and we demonstrate some of them in the dissertation. Along the way, we look at many other related problems in the dissertation. As an example, we provide initial results about the issue of robustness of a distributed system design to a malfunctioning agent. This notion is currently lacking in the control and estimation community, but has to be a part of any effective theory for designing networked or distributed systems.

The main topic of this thesis is related to the state of the art in designing cryptographic primitives from a hardware point of view. A special emphasis is dedicated to low-power/low-energy CMOS design. A set of solutions is proposed including an LFSR based stream cipher with self-synchronizing capabilities, a new memory-less Rijndael block cipher architecture and a public key scheme in the class of discrete logarithm. The former is based on arithmetic in large finite field, mainly Galois extension field GF(2‴). These solutions are droved using low-energy techniques, in order to decrease both the switching activity and the total delay. The fundamental motivation supporting this work, is to demonstrate that practical solutions can be obtained for implementing such complex primitives in large scaled circuits, that arc at once, high performance architectures (low-power, high-speed) and cryptographicaly strong, using the well known trade-off between area-speed or area-power. Security constraint has been duly considered, mainly by increasing the key-size. In this work, we explore the general aspects of designing the above mentioned cryptographic functions. We give an extensive survey of some cryptographic primitives from the hardware point of view and expose their security properties. The thesis favours stream cipher and public-key schemes, as currently the most promising advance to capture the notion of key generation and establishment and data bulk encryption. One contribution is the convenient notation for expressing cryptographic self-synchronizing stream ciphers SSSC schemes and our SSMG proposal, a scheme based on packet fingerprint identification, that relies on keyed cryptographic hash function to achieve the security requirements. We maintain an important distinction between hardware implementation and algorithm's security, because the security of cryptographic primitives cannot be based on mathematically strong functions only but requires an extensive cryptanalysis at different levels including the application. This causes a concern for a formalization of the security of an implemented cryptographic primitive. Nevertheless, while some schemes arc well known to be secure such as DL based public key schemes and enough cryptanalyzed such as the new standard Rijndael, some security aspects of the SSMG are discussed. A part of this work studies the specific aspects related to hardware implementation of Rijndael block cipher, the new standard designed to be a substitute for DES. An efficient architecture is developed targeting FPGA implementation, by simply avoiding memory blocks dedicated to the implementation of S-boxes and replacing them by on-chip forward computation using composite Galois field. This technique helps to reduce considerably the amount of hardware required at the cost of little increase of the switching activity. The main conclusion is that, while security constraint of cryptographic primitives increases the hardware complexity and reduces the performances, practical solutions exist for reducing such complexities while keeping or increasing the level of security. Nevertheless, major open questions remain both for a firm theoretical foundation and the proper cryptanalysis of certain solutions.

Oxide-based metal-insulator-metal structures are of special interest for future non-volatile resistive switching memory, also known as resistive random-access memory (ReRAM) [1]. In such cells, resistive switching in the oxide layer is widely believed to be caused by the electric‐field‐driven motion and internal redistribution of oxygen ions (or vacancies) with filament region, resulting in valence change on the cation sublattice [1]. There are very special oxide-material groups which undergo a reversible topotactic phase transition between the insulating brownmillerite and conducting perovskite structure upon the redox processes [2]. Recently, we introduced a topotactic phase changing brownmillerite SrMO2.5 (M = Co, Fe, etc.) as a novel material platform to harness exceptional oxygen ion transport properties for resistive switching memory devices for the first time [3,4]. Accordingly, we were able to demonstrate a promising resistive switching performance with high endurance (> 106 cycles), fast switching speed (10 ns), and high uniformity in key switching parameters [5,6]. By using X-ray absorption spectromicroscopy and in site TEM, we could prove that the resistance change is indeed caused by a reversible topotactic phase transition between an insulating SrFeO2.5 brownmillerite and a conductive SrFeO3 perovskite phase [7]. By engineering the ordered oxygen vacancy channels in brownmillerite structure, we further demonstrated complimentary resistive switching and synaptic memory behavior in the SrFeOx memristive devices [8]. Beyond resistive switching, our results demonstrated a clear path to tune the ionic controlled functionalities in the multiphase oxides by electrical bias at the nanoscale level, which is highly interesting in the field of magnetoelectric and spintronic device applications. Reference [1] R. Waser, R. Dittmann, C. Staikov, K. Szot, Adv. Mater. 21 (2009) 2632–2663. [2] H. Jeen, W.S. Choi, M.D. Biegalski, C.M. Folkman, I.C. Tung, D.D. Fong, J.W. Freeland, D. Shin, H. Ohta, M.F. Chisholm, H.N. Lee, Nat. Mater. 12 (2013) 1057–1063. [3] O.T. Tambunan, et. al. Appl. Phys. Lett. 105 (2014) 063507. [4] V.R. Nallagatla, C.U. Jung, Appl. Phys. Lett. 117 (2020). [5] S.K. Acharya, R.V. Nallagatla, O. Togibasa, B.W. Lee, C. Liu, C.U. Jung, B.H. Park, J.Y. Park, Y. Cho, D.W. Kim, J. Jo, D.H. Kwon, M. Kim, C.S. Hwang, S.C. Chae, ACS Appl. Mater. Interfaces 8 (2016) 7902–7911. [6] S.K. Acharya, J. Jo, N.V. Raveendra, U. Dash, M. Kim, H. Baik, S. Lee, B.H. Park, J.S. Lee, S.C. Chae, C.S. Hwang, C.U. Jung, Nanoscale 9 (2017) 10502–10510. [7] V.R. Nallagatla, T. Heisig, C. Baeumer, V. Feyer, M. Jugovac, G. Zamborlini, C.M. Schneider, R. Waser, M. Kim, C.U. Jung, R. Dittmann, Adv. Mater. 31 (2019) 1903391. [8] V. Raveendra Nallagatla, J. Kim, K. Lee, S. Chul Chae, C. Seong Hwang, C. Uk Jung, Cite This ACS Appl. Mater. Interfaces 12 (2020) 41740–41748.