Class and module in SOFL

Standardization of Formal Specification Languages

Many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we proposed an eclectic approach to incorporate Z(Zed) formal language and ‘Statemate MAGNUM’ which is formal method tools using Statechart. Also we applied the proposed method to safety-critical railway signaling systems for the formal requirement specification and analyzed the specification results.

The complexity of designing concurrent and highly-evolving interactive systems has grown to a point where system verification has become a hurdle. Fortunately, formal verification methods have arrived at the right time. They detect errors, inconsistencies and incompleteness at early development stages of a system formally modeled using a formal specification language. -calculus (Milner, 1999) is one such formal language which provides strong mathematical base that can be used for verifying system specifications. But manually verifying the specifications of concurrent systems is a very tedious and error-prone work, especially if the specifications are large. Consequently, an automated verification tool would be essential for efficient system design and development. In addition, formal verification tools are vital ingredient to fully harness the potential of component-based software composition. The authors developed such an automated verification tool which is highly portable and seamlessly integrates with the visualization, reduction and performance evaluation tools introduced (Ahmad & Rahimi, 2008; Rahimi, 2006; Rahimi et al., 2001, 2008) to provide a comprehensive tool for designing and analyzing multi process/agent systems. Open-Bisimulation (Sangiorgi, 1996) concept is utilized as the theoretical base for the design and implementation of the tool which incorporates an expert system implemented in Java Expert System Shell (JESS) (Friedman-Hill, 2003).

In Wide Area Networks (WANs)inconsistencies among the security policies of Administrative Domains (ADs) may cause severe security flaws. Recently, security policies are written in natural language and as they get more complicated, even for an expert it might be impossible to detect such inconsistencies. However, when a formal language is used, it might be possible to make verification of security policies by automated theorem proving tools. Due to the existence of mobile devices such as laptops, PDAs and mobile agents, we need a formal language that is capable of defining the concept of mobility. In this paper, we extend Mob adtl [1] according its refinement methodology to obtain a formal policy specification language for an 802.11 WLAN with enhanced security network.

Traditional structured analysis and design methods have been criticized because the methods lack formality to provide a design for rigorous development. Several approaches have been developed for verifying a design by integrating traditional structured analysis and design methods with formal specification languages. However, the integration of traditional structured analysis and design methods with formal specification languages may confuse the problem definition and understanding with the attempt to define system structures and algorithms in the design phase. In addition, formal specification languages may add complexity to the design due to the complexity of the language syntax and semantics. In this paper, we are presenting an approach to verification of a structured design in HOS without using formal specification languages. Rules for the partial and total correctness of the design are also discussed.

The Unified Modeling Language (UML) has become a widely adopted standard in the software development industry. Unfortunately, the UML is a semi-formal language which lacks precisely defined constructs. Z language is a formal specification language. Formal languages are used to ensure that systems meet regulations and standards. This paper aims to reduce risks associated with software development and increase safety and reliability. This goal is achieved by formalizing the syntax of (a sub-set of the popular UML diagrams (Use Case diagram, Class diagram, and State Machine diagram) using Z specifications.

Requirements engineering or analysis is normally seen as the process by which software requirements are identified and specified, and has been described as a ‘process of discovery, refinement, modelling and specification’ [36] . System modelling is a useful tool in this process. We can create models to express our understanding of a current system problem, to identify areas for change or to describe the final product to be built. They permit the partitioning of complex system problems into smaller and more manageable units, and can be used as a basis for communication and validation with the client. Many of the modelling approaches use semi-formal diagramming techniques resulting, for example in data flow diagrams and entity relationship diagrams, and may be supported by explanatory text . However these approaches lack the well defined and formal syntax that permits precise analysis, and models expressed in these terms are open to possible misunderstanding and ambiguity. At some point we need to express the model more formally and to subject it to precise and rigorous analysis. The use of a formal specification language as a modelling tool provides a possible way to achieve this.

Translating meaning representations to behavioural interface specifications

In this work the protocol WorldFIP for industrial communication networks, is specified with the formal specification language LOTOS. This specification is the foundation of new work lines such as efficiency analysis of WorldFIP performance with simulations in critical applications, the generation of benchmark patterns for conformance tests of WorldFIP communications equipment, and the proposal of new advances in the fieldbus area. Standardization institutions can benefit largely by this implemented methodology of formal specification, because some uncertainties in their description issues can be detected easily during the standard development, if a formal specification language is used at this stage.

Ubiquitous embedded systems are revolutionizing our daily lives. Whole systems on a chip deliver unprecedented computation power at ever decreasing costs. However, their complexity makes their design with traditional RTL-based flows extremely challenging. Complexity in such systems arises not only from the diversity of the technologies, from RF front-ends to baseband DSP software, that must be integrated on-chip, but also from the fact that such systems must be increasingly built from parts that have been designed separately and using different tools and flows. High abstraction levels and component reuse are essential. Often such systems are highly networked and rely on sophisticated communication mechanisms. Architectural design and performance analysis of such networked system-chips is a crucial part of the embedded system design process.Two basic methods for tackling the growing complexity of system-on-chip design are emerging. Formal specification and design methods, and platform-based design. Formal methods are essential to capture precisely the designer intent at the highest possible level of abstraction, and to guide him down towards an implementation. Design errors are reduced by the use of synthesis techniques, as well as by the availability of a variety of validation techniques. Moreover, the orthogonalization of concerns (e.g., computation vs. communication, function vs. architecture) promotes extensive reuse of both parts of an application (derivative designs) and of previously used architectures.A platform in this context is the precise specification of a high-level implementation target that supports both a variety of lower level implementations, and a variety of higher-level applications. A classical example is the PC, that has supported an explosive growth of both applications and implementations. In embedded systems-on-chip platform clearly need to be application-specific. A typical platform includes one or more processors, memory, one or more bus hierarchy levels, and peripherals devoted to application-specific functions (e.g., MPEG decoding, filtering, A/D conversion, ...). Mapping to a platform involves identifying which portions of the application will be implemented on each computation and communication resource. Communication must be refined from high-level primitives (e.g., FIFOs) down to platform primitives (e.g., interrupts, memory buffers, ...). Functionality must be synthesized and scheduled based on platform-specific cost, memory and performance constraints.In this tutorial we will cover both aspects in detail, illustrating first the languages and Models of Computation available to the system-level designer to capture precisely and unambiguously the requirements. We will discuss for what application domain and platform each language is most appropriate, focusing mostly on platform-independent languages and MOCs, since they support the greatest freedom in mapping choice. We will then discuss how the architecture of the platform, and the services it offers to the application designer, can also be formally and compactly captured and specified. We will show how the mapping paradigm can be used to select an implementation for the functional blocks and their communication, and how simulation and implementation methods can be derived automatically. In particular, we will describe how software estimation and synthesis for reactive real-time systems can be competitive with hand design, while retaining the ease of re-use typical of high-level specifications.In the next part of the tutorial, we will establish the importance of on-chip communication architectures in determining the performance of System-on-Chips (SoCs). We will track several on-chip communication architectures that are in use today, including different types of bus architectures, token ring architectures, and crossbar switches. We will analyze the performance of the existing communication architectures under different classes of on-chip communication traffic. We will also describe novel on-chip communication architectures that are being developed to satisfy the growing needs of fast and concurrent on-chip communication in very high-performance systems like network processors. Next, we will describe efficient methodologies that can be used to analyze and design customized on-chip communication architectures for new application-specific platforms, as well as optimally map an application's communication requirements to the communication architecture present in an existing platform. We will also discuss reconfigurable on-chip communication architectures that allow runtime adaptation of the communication protocols to changing communication demands of the platform. Besides performance, we will analyze the energy consumed by on-chip communication architectures, and describe techniques to minimize such energy consumption. Lastly, we will analyze the impact of deep sub-micron technologies on SoC communication, and discuss the needs for development of noise-aware on-chip communication.

The two most critical phases of SDLC are the specification and the designing phase as they involve the transformation of the semantics from real world domain to computer software systems. Unified Modelling Language (UML) has been accepted as blue print for design and specification of software critical systems. But, UML structures have the weakness in preciously defining the semantics of a system. Any misinterpretation in safety critical system’s specification may risks loss of lives. Formal methods are mathematical tools and techniques which are proven very adequate, principally, at requirement specification and design level. However, formal methods are not welcomed because of rigorous use of mathematics. Therefore, a bridge is required between UML and formal methods to overcome the above insufficiencies. The endeavour of this paper is to propose a new approach by integrating UML and Z notation, a formal specification language. The main focus of this paper is on transforming the UML diagram: use case diagram, class diagram and sequence diagram to Z Schema for capturing both the syntax and semantics, particularly for safety critical system. The resultant formal model of the approach are analyzed and verified by using Z/Eves tool.

For safety critical systems, hardware is often preferred over software because it is easier to achieve safety goals in hardware alone and because hardware is considered more reliable than software. But as systems become more complex, software solutions will also be important. Here we demonstrate, using a simple example, that formal methods are a useful tool for developing software specifications for safety critical systems, since they reduce ambiguity in the design and can be proven consistent. Using formal methods for specifications will enable the development of dependable, high-performance, reliable hardware/software safety critical systems. The method we describe is the first step in our work to establish a hardware/software development process for safety critical systems.

In most studies of bridging between informal specifications, formal specifications are transformed from informal specifications after completion of specification of the whole system. Most of these formal specifications are used for rigorous study of the system in question, consistency checking, verification of behavior or support system synthesis. During the process of system specification, the strength of formal and informal methods are not complementing to each other. We identified a new specification approach which makes formal methods and informal methods complement each other to a greater extent. This new method interweaves formal methods with informal methods. We find out that this method leads to better quality of specifications, facilitate better changes management and maintenance. This is particular useful during initial specification of systems which is the first stage of specifying informal world in some formal languages. We report our preliminary findings of this novel approach in this paper and exemplify our approach with an example in JSD and CSP.

The visual modeling language UML embodies object-oriented design principles.It provides a standard way to visualize the design of a system. It exploits a richset of well-defined graphical notations for creating abstract models. However,the power of UML is lessened through partially specified formal semantics. Indeed, UML notations are semi-formal and do not lead to fully formalized andexecutable semantics. Fortunately, UML diagrams are prone to early formalization. Formal methods are a valuable tool that can help overcome the UMLconstructs’ shortage of firm semantics. It is a powerful way to ascribe precise semantics to the graphical notations used in UML diagrams and models.Our work aims to support the semantics of the UML Interaction Overview Diagram. It introduces an approach to leveraging the strengths of the MaudeRewriting Logic language as a formal specification language. The proposal relies on a model-driven engineering approach. It aims to automate the UMLInteraction Overview Diagram’s mapping to a Maude language specification.The Maude language and its linked tools, including the Maude Model Checker,are used to analyze and verify the resulting Maude specification. Finally, anapplication example shows the feasibility and benefits of the proposed approach.

Communication systems can be characterized by high reliability requirements, complexity in development, and distribution of processes and resources. In developing these kinds of systems, formal methods can be fruitful in achieving high quality of resulting systems. LOTOS, a formal specification language, allows us to write models of the system in an abstract but rigorous manner. In this paper, we present a behavior compiler that supports rapid prototyping by generating C++ code from LOTOS behavioral specifications. Execution of the generated code allows us to detect analysis and design errors at the early stage of system development life cycle.