Clock distribution networks in synchronous digital integrated circuits

Clock distribution networks synchronize the flow of data signals between data paths, and the design of these networks can dramatically affect system wide performance and reliability. The field of clock distribution design can be grouped into a number of subtopics: 1) circuit and layout techniques for structured custom VLSI systems; 2) the automated synthesis of clock distribution networks with application to automated synthesis of clock distribution networks with application to automated placement and routing of gate arrays, standard cells, and larger block-oriented circuits; 3) the analysis and modeling of the timing characteristics of clock distribution networks; and 4) the specification of the optimal timing characteristics of clock distribution networks based on architectural and functional performance requirements. Each of these areas is described and summarized. Future trends are discussed. >

Optimization of the performance of a high­speed synchronous digital system requires tight control of the timing skew within a clock distribution network (CDN). Techniques for distributing the optical clock signals in a single-stage CDN have been suggested in [1,2] to reduce the timing skew, and the fanout is found to be much larger than that obtained from an electronic CDN. In this paper, we investigate the enhancement of fanout when optical amplifiers, which could either be semiconductor laser amplifiers [3] or fiber amplifiers [4], are introduced in a CDN.

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technology's corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation

The idea of combining high-speed digital cores, memory arrays, analog blocks, and communication circuitry onto a single chip has led to a whole new design era of System on Chips (SoCs). The clock distribution network is one of the important issues in SoCs that consumes a significant portion of the total performance. In this paper, a flexible capacitance is used to make the clock distribution network more flexible for designing the clock distribution network. Therefore, if some IP (intellectual property) cores are changed in the system, we do not need to redesign the overall clock distribution network. This new approach facilitates the clock timing and synchronization of IPs so that IPs can be inserted or removed from the distribution network without affecting the whole performance of a SoC. This design uses efficiently the available resources and maintains clock signal integrity. The experimental results confirm the efficiency of the proposed design.

In integrated circuits, clocking system consumes a colossal portion of chip power, which includes switching activities of flip-flops, latches, clock distribution networks. Power gating and clock gating are two of the most effective techniques that is applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits. Power gating is essentially for reducing leakage power by switching off power supply to the nonoperational power domain of the chip during certain mode of operation. Header and footer switches, isolation cells and State Retention Flip Flops (SRFFs) used for implementing power gating. Clock gating is for reducing dynamic power by controlling switching activities on the clock path. Generally, Gate, Latch, or FF based clock gating cells used for implementing clock gating. The combined use of the two solutions, however , possess some challenges in terms of practical integration of the required control logics and power/timing overhead associated to it. Here we present an analysis in Cadence virtuoso tool using 90nm technology using a simple PIPO (parallel in parallel out) shift register. This project specifically targets the combined application of clock and power gating techniques.

<p>This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz. </p>

Recursive bisection is a popular approach for large scale circuit placement problems, combining a high degree of scalability with good results. In this paper, we present a bisection-based approach for both standard cell and mixed block placement; in contrast to prior work, our horizontal cut lines are not restricted to row boundaries. This technique, which we refer to as a fractional cut, simplifies mixed block placement and also avoids a narrow region problem encountered in standard cell placement. Our implementation of these techniques in the placement tool Feng Shui 2.6 retains the speed and simplicity for which bisection is known, while making it competitive with leading methods on standard cell designs. On mixed block placement problems, we obtain substantial improvements over recently published work. Half perimeter wire lengths are reduced by 29% on average, compared to a flow based on Capo and Parquet; compared to mPG-ms, wire lengths are reduced by 26% on average.

The aggressive scaling of CMOS technology toward nanometer lengths contributed to the surfacing of many effects that were not appreciable at the micrometer regime. Among them, Inverted Temperature Dependence (ITD) is certainly the most unusual. It manifests itself as a speed up of CMOS gates when the temperature increases, resulting in a reversal of the worst-case condition, i.e., CMOS gates show the largest delay at low temperatures. On the other hand, for metal interconnects an high temperature still holds as worst case condition. The two contrasting behaviors may invalidate the results obtained through standard design flow which do not consider temperature as an explicit variable in their optimizations. In this paper we focus on the impact of ITD on clock distribution networks (CDN), whose function is vital to guarantee the synchronization among physically spaced sequential components of digital circuits. Using our simulation framework, we characterized the thermal behavior of a clock tree mapped onto an industrial 65nm CMOS technology and obtained using a standard synthesis tool. Results demonstrate the presence of ITD at low operating voltages and open new potential research scenarios into the EDA field.

As clock frequency in CPU designs increases, skew management in the clock network becomes more important. Clock skew reduces the performance of the design and is a function of load, network distribution across the die, and device mismatch as well as temperature, and voltage gradients. This digital deskewing circuit can be used in microprocessor designs to equalize two clock distribution spines by compensating for these mismatches and gradients. The circuit is composed of delay lines in both spines of the microprocessor clock distribution network, a phase detection circuit, and a controller. The phase detection circuit determines the phase relationship between the two spines and generates an output based on the phase relationship. The controller takes the phase detection information and makes a discrete adjustment to one of the delay lines that was determined by the controller to require adjustment.

Wire shaping of RLC interconnects

This paper presents a compiler from a standard Hardware Description Language (Verilog HDL) to an asynchronous Control Unit and a synchronous Data Path. The Control Unit, specified as a Signal Transition Graph, can be implemented using research-oriented asynchronous synthesis tools. The Data Path, specified using the Synthesizable Subset of Verilog, can be implemented using state-of-the-art commercial synchronous synthesis tools. Our compiler integrates in a fully automated manner source parsing, control/data splitting, managing the design and inserting matched delays for data bundling constraints. It can be used to produce asynchronous designs in an Application Specific Integrated Circuit design style, since the result is a netlist of standard cells ready for physical design. We describe a simple example of compilation and its results, and we discuss some outstanding issues in the domain of asynchronous Control Unit synthesis.

During the Computer Aided Physical Design Cycle and specifically for high-performance VLSI circuits, on-chip power density plays a major role. The catalyst factors are increased scaling of technology, increasing number of components, higher frequency and bandwidth. The consumed power is usually converted into dissipated heat, affecting the performance and reliability of a chip. Moreover, recent trends in VLSI design entails the stacking of multiple active layers into a monolithic chip. These 3D chips have significantly larger power densities than their 2D counterparts. In this paper, we consider the placement of standard cells and gate arrays (modules) under thermal considerations. Our contribution includes a novel algorithm for placement of the gates or cells in the different active layers of a 3D IC such that: (i) the temperatures of the modules in each of the active layers is uniformly distributed, (ii) the maximum temperatures of each of the active layers is not too high, (iii) the maximum temperatures of the layers vary in a non-increasing manner from bottom layer to top layer to ensure an efficient heat dissipation of the whole chip. Experimental results on randomly generated and standard MCNC and ISPD benchmark instances are quite encouraging.

In this paper an algorithm for multiple way network partitioning is developed extending the idea of two-way partitioning. Multi-level gain concept is adopted in this algorithm. Results from several examples run agree with the fact that direct r-way partitioning gives rise to lower cutset than hierarchical partitioning. This multi-way partitioning approach is used for Standard cell placement, such that each partition corresponds to each row of a Standard cell based chip. Finally successive rows of cells for placement are found such that number of vias is minimised. Experimental results of several placement problems show that the approach is both effective and efficient in yielding smaller cutset and hence better placement.

The DC distribution network based on the hybrid modular multilevel converter (MMC) has the ability of active current-limiting control, which plays an active role in fault clearing of distribution network. However, the fault characteristics of the DC distribution network become complicated because of the active current-limiting control. It brings new problems to the fault detection and judgment of relay protection. According to the structural features of the hybrid MMC, the start-up strategy and control objectives of the active current-limiting control are analyzed in this paper. The improvement suggestions are put forward to maintain the operational safety of the power grid, as well as meet the application requirements of the relay protection. Moreover, The characteristics of the short-circuit current of the DC distribution network are analyzed based on the active current-limiting control. Meanwhile, the influences on the relay protection are estimated. Finally, the effectiveness of the proposed current-limiting control strategy and the correctness of the fault characteristic analysis results are verified by simulation tests.

Hybrid data-driven method for distribution network topology and line parameters joint estimation under small data sets