Wire shaping of RLC interconnects

This paper presents a novel method to reduce the crosstalk induced delay in coupled carbon nanotube (CNT) bundle based through silicon vias (TSVs). A unique structure of mixed CNT bundled (MCB) TSV is proposed, wherein multi-walled CNTs (MWCNTs) are placed peripherally to the centrally located single-walled CNTs (SWCNTs). An electrical equivalent model is employed for analyzing these MCB configurations. The analysis demonstrates that a significant reduction in propagation delay and crosstalk induced delay is achieved for a larger number of peripheral layers containing MWCNTs. Moreover, the crosstalk reduction is prominently higher for MWCNTs with more number of shells in longer TSVs. For TSV heights from 30 to 120μm, an average reduction of out-phase, in-phase and propagation delays of 17.54%, 19.73% and 14.45%, respectively, is observed using novel MCB instead of conventional SWCNT bundle based TSV.

The scaling process of the conventional 2D‐planar metal‐oxide semiconductor field‐effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub‐20 nm region. In this work, the FinFET structure is implemented in 1‐bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass‐Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1‐bit FinFET‐based full adder in 16‐nm technology is benchmarked against conventional MOSFET‐based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model‐Common Multi‐Gate (BSIM‐CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power‐delay‐product (PDP), and energy‐delay‐product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1‐bit FinFET‐based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1‐bit FinFET‐based full adder of CPL, giving the best overall performance due to its high‐speed performance and good current driving capabilities.

A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the traditional quadratic dependence of the propagation delay on the length of an RC line approaches a linear dependence as inductance effects increase. The closed form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. An RC model as compared to an RLC model creates errors of up to 30% in the total propagation delay of a repeater system. Considering inductance in repeater insertion is also shown to significantly save repeater area and power consumption, The error between the RC and RLC models increases as the gate parasitic impedances decrease which is consistent with technology scaling trends. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.

The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> value of the phase skew from 4.16 to 2.25 ps.

This brief proposes lower power lower delay design for CMOS tapered buffers. A slight increase in the threshold voltage is shown to have an exponential effect in reducing the total power dissipation. The corresponding increase in the propagation delay is compensated for by increasing the number of buffer stages such that there is still an overall significant reduction in the total power dissipation. As compared to the constant threshold voltage design based on a cost function of PT <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the proposed scheme can lead to either a power dissipation reduction of about 70% while maintaining the same delay, or up to 30% in power dissipation with 10% propagation delay reduction, respectively, in 65-nm technology with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> = 1 V, minimum size gate capacitance, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 1.5 fF, and minimum size output capacitance, C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> = 1 fF. Closed-form expressions that give the optimum threshold voltage and number of stages are presented.

This paper presents the design of high speed multiplier and squaring architectures based upon ancient Indian Vedic mathematics sutras. In existing Vedic multiplier architectures, the partial product terms are computed in parallel and then added at the end to get the final result. In this work, all the partial products are adjusted using concatenation operation and are added using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squaring modules. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only, the designed multiplier offers significant improvement in speed. The designed architectures are realized using Xilinx Spartan-3E FPGA. The comparison shows the 28.72% and 38.59% reduction in propagation delay for the designed 32-bit multiplier as compared to the existing multiplier designs.

Low-latency transmission is necessary for optical transmission systems, and a reduction in propagation delay of 1 μs in an optical fiber is effective. We investigated the tradeoff between latency and loss among silica-glass solid-core optical fibers. The decreases in the core radius and core refractive index are known to reduce group delay of pure silica core fibers. We experimentally evaluated the Rayleigh-scattering-loss and imperfection-loss characteristics of pure silica core fibers with smaller radius and fluorine (F)-doped core fibers. A decrease in the pure-silica-core radius has a non-negligible impact on imperfection-loss increase compared with on Rayleigh-scattering-loss increase induced by F-doped core and clad. We show the potential of F-doped core designs for reducing propagation delay of 1 μs after an over 500-km long transmission while suppressing the impact on loss increase.

The unique feature of the dual mode logic (DML) model is its switching ability between static and dynamic modes of operation according to the system required. In dynamic mode, the DML model achieves high performance along with increased power dissipation, while in static mode DML models attain low power with moderate performance. In this paper, we analyzed DML model functioning in different regions to realize the trade-off between power and propagation delay. In addition, to that we have proposed the multi-threshold DML (MTDML) model. Its robustness to supply voltage and sensitivity to the process temperature variations are presented. Simulations are performed at 16 nm and 22 nm technologies using predictive technology model (PTM) files. Simulation results show that MTDML has reduced propagation delay and increased power dissipation at the low threshold voltage.

The optimum tapered structure for RLC interconnect to minimize transient power dissipation is determined. Wire tapering can reduce the power dissipated by a circuit by up to 72% as compared to uniform wire sizing. An analytic solution to determine the optimum tapered structure exhibits an error of less than 2% as compared to SPICE

LEO satellite communications systems are expected to enter service in the near future. They will use: 1) low altitude orbits in which satellites move at high angular velocities over the earth and 2) multiple beams to establish communication links. Beam-to beam and satellite-to-satellite handoffs need to be employed. This paper analyzes and discusses duration of dwells between such hand-offs for two systems, one designed for L-band use which communicates to earth terminals at elevation angles as low as 10° and the other designed for Ka-band use which communicates to earth terminals at elevation angles of 40° and greater. Also an analysis to determine the minimum and maximum propagation delays over the intersatellite links between the satellites used in the constellations for both systems is performed. Conclusions are that the beams should be adjusted in beamwidth to equalize the dwell durations during a satellite pass, especially for systems operating at low elevation angles, that scanning beams which point at fixed earth cells during a satellite pass are desirable for systems operating at high elevation angles, that maximum propagation delays and propagation delay variations encountered are significantly smaller for the high elevation angle system principally because of the large number of satellites needed in its constellation and that datagram packets must be used to establish virtual circuits over the systems. The maximum end-to-end propagation delays encountered are far less than those encountered over geostationary orbit satellites and, provided delays in processing the signal for transmission are not large, the service quality should differ little from that provided over terrestrial and submarine fiber cable links.

We previously used back propagation neural network (BPNN) with the meteorological factors of the receiver point to establish a model for predicting propagation delay of Loran-C signal over a short distance. Nevertheless, for a long propagation path, it is not proper to use only the meteorological factors of the receiver point. In this letter, a propagation delay prediction model that considers multiweather and multipoint was established by using a more suitable generalized regression neural network (GRNN) over a long distance. We first compared three meteorological factors of six points on the propagation path, and found that they have obvious differences. Then, a propagation delay prediction model based on three meteorological factors of the six points is established with GRNN. Finally, the further comparison shows that on the one hand, GRNN is more suitable to establish the prediction model of propagation delay than BPNN; on the other hand, more points on the propagation path are considered, and the prediction accuracy of the model is higher.

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier design (ASIC) using Vedic Mathematics is presented in this paper. The idea for designing the multiplier and adder/sub-tractor unit is adopted from ancient Indian mathematics “Vedas”. On account of those formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay in comparison with DA based architecture and parallel adder based implementation which are most commonly used architectures. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using standard 90nm CMOS technology. The propagation delay of the resulting (16, 16)×(16, 16) complex multiplier is only 4ns and consume 6.5 mW power. We achieved almost 25% improvement in speed from earlier reported complex multipliers, e.g. parallel adder and DA based architectures.

The enhanced long-range navigation (eLoran) system serves as an important backup method for the global navigation satellite system (GNSS) system. In long-distance transmission scenarios, the signal propagation delay of the eLoran system is affected by fluctuations in meteorological factors along the path. Regarding these issues, such as the potential timing system errors caused by meteorological factors and the limitation on the accuracy of the timing system, in this paper, an innovative prediction model is proposed to predict the propagation delay data by fusing the propagation delay data of multiple differential reference stations on the path and the path-weighted meteorological data. By collecting and processing actual data, four types of prediction tasks were designed. Comparative analyses of the prediction performance of eight common models were conducted on a unified dataset. The results show that the Pucheng–Zhengzhou path-weighted ten-factor back-propagation neural network (PZWT-BPNN) model performs the best, achieving a balance between prediction accuracy and training efficiency. This model effectively suppresses the timing errors caused by meteorological fluctuations and improves the prediction accuracy of the propagation delay of the system, providing corresponding technical support for key fields such as low-altitude economy and transportation.

In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the RC based approaches but can accommodate inductance. These new expressions are derived based on a generalized driving point admittance. The generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. Another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. It is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an RLC interconnect load. Simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an RLC model in realistic interconnects. On the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to SPICE.

Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are logarithmic in the wire lengths. These conditions are imposed by area requirements and the velocity of light.