Including inductance in static timing analysis

The role of network structure and time delay in a metapopulation Wilson--Cowan model

<div class="htmlview paragraph">Transceiver propagation (also known as wrap-around, loop-back, or round-trip) delay time and output voltage slew rates have a profound impact upon bit timing. Excessive propagation delay produces an error in the generated symbol time that may cause a bit timing error in a receiving node. Any difference between the compensation time of the protocol handler and the transceiver propagation delay will be seen in the transmitted pulse time. The larger the gap, the longer the transmitted bit time. The bit distortion increases even further if the receiving node is operating in a ground offset voltage with respect to the transmitter. Bit distortion is exacerbated as well when the output voltage slew rates are too slow. When the slew rates are too slow, the receiving bit time may be too short in a positive ground offset voltage condition and too long in a negative ground offset voltage condition. Either of these issues may also contribute to the inability of the protocol handler to successfully arbitrate the bus. The transmitting node may diagnose a short-to-ground condition and cause glitches on the bus.</div> <div class="htmlview paragraph">Transceiver propagation delay must be designed to be compatible with the compensation capabilities of the intended protocol handler(s). Output voltage slew rates must also be understood so that the total contribution of these two errors does not result in the inability to transmit successfully into maximum ground offset conditions.</div>

The main cause of the absolute positioning error in the Loran‐C system is in the occurrence of the propagation time delay error caused by the fact that the propagation speed of the pulse signal on the actual propagation path is different from that assumed in the formation of the Loran‐C maritime chart. The propagation path characteristics not only cause the propagation time delay of each received pulse signal but also generates waveform distortion in the received pulse. Hence, it is possible to estimate the propagation delay time by means of this waveform distortion. At present, a measure of the distortion of the pulse waveform distortion of the Loran‐C is envelope to cycle difference (ECD). In this paper, as a new measure for the pulse‐wave distortion to estimate the propagation time delay, CHACLE, or change of half‐cycle length, is proposed. A method for correction of the absolute positioning error is provided based on the estimation of the propagation time delay from the measures of the wave‐form distortion (CHACLE and ECD) by means of the simplified propagation path for an easy analysis and of the general propagation path. It is demonstrated that CHACLE is superior to ECD in terms of the effect of correction. Further, to confirm the validity of the correction method proposed in this paper, the present method is applied to a propagation path model resembling the mixed propagation path used in the United States to estimate the pulse time delay. It is confirmed that the absolute positioning error can be reduced to less than about 20 percent.

Modern electronic systems increasingly operate across multiple voltage domains, necessitating robust and efficient level shifter (LS) circuits to ensure reliable inter-domain communication. In low-power digital applications, minimizing propagation delay and transition time is critical for achieving high-speed and energy-efficient operation. This work presents a high-performance level shifter optimized for integration within Li-ion battery charger systems. The proposed design achieves a substantial reduction in propagation delays from 0.15 to 0.09062 ns while preserving signal integrity. When integrated with a gate driver, the overall structure exhibits a propagation delay of 0.20468 ns and a transition time of 0.014 ns, marking a significant improvement from the previous 0.036 ns. Furthermore, the proposed circuit occupies only 0.00039 mm² of silicon area, representing a 92% reduction compared to prior implementations (0.05 mm²). The complete design was implemented using Taiwan semiconductor manufacturing company (TSMC) 130 nm complementary metal–oxide– semiconductor (CMOS) technology, with both schematic simulation and layout carried out in the Cadence Virtuoso design environment. These results underscore the potential of the proposed solution for compact and high-efficiency system-on-chip (SoC) battery management applications.

The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing constraints. This is due to the inability of the logical effort model in capturing I/O coupling and input ramp effects that distinguish the transition time from the propagation delay. Using an analytical modeling of the supply current that flows in simple gates during their switching process, this paper introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect. Validation of this model is performed on 130-nm STMicroelectronics technology. A compact representation of CMOS library timing performance is given as a possible application of the proposed model. The choice of sampling points to be used in look-up tables as representative steps of the design range is also discussed

This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a post-processing step, wire width optimization under an accurate higher-order delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.

This paper is devoted to the performance optimization of an aerial manipulation system composed of a Flettner-helicopter and 7 DoF manipulator. With experiments we demonstrate that the time delays in signal propagation between perception and actuation modules play an important role for the overall performance of an aerial manipulator system using visual servoing. We present an approach for estimation of the perception-action time delay and its active compensation based on the predicted motion of the manipulator end-effector.

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i/sub 0/ (or load resistor R/sub L/) for a transistor of a certain emitter area when driven by a source of a voltage swing (/spl Delta/V) and slew time (t/sub r/). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits. >

Slow light is demonstrated in the cascade structure of an erbium-doped fiber with two forward propagation pumps. The results of the numerical simulation of the time delay and the optimum modulation frequency complement each other. The time delay and the optimum modulation frequency depend on the pump ratio G (G = ). The discussion results of this paper show that a larger time delay of slow light propagation can be obtained in the cascade structure of Er3+-doped optical fibers with dual-frequency laser pumping. Compared to previous research methods, the dual-frequency laser-pumped cascade structure of an Er3+-doped optical fiber is more controllable. Based on our discussion the pump ratio G should be selected in order to obtain a more appropriate time delay and the slowdown of group velocity.

Wire shaping of RLC interconnects

Time delay estimation is one of the key steps in target localization and high resolution imaging in Through-Wall-Radar signal processing procedure. In some typical TWR scenarios, electromagnetic wave propagates through two layers with different physical properties parameters. Traditional methods for the time-delay calculation in such situations are usually using three-dimensional searching algorithm or solving three variables equation of four times and tedious and time-wasting. This paper presents a new fast time-delay algorithm for electromagnetic wave propagating through two layers. An equation of two lateral distances through the walls can be established because of the fact that incident angle at upside of the walls equals to refracting angle at the downside of the walls. Total propagation path and time delay can be calculated by the two lateral distances subsequently. Simulating experiments prove the new algorithm is suitable for real-time time-delay calculation in TWR signal processing.

Time delay estimation is very important in many applications such as radar, sonar, communication, geological exploration, biomedical engineering, etc. We propose a SINC filtering algorithm (SFA), i.e., one based on the sinc function. The algorithm can get an accurate time delay estimate with little or no prior knowledge about the statistical characteristics of the received signals. SFA is based on the theory that time delay estimation can be transformed to the parameter estimation of a SINC filter, and the time delay estimate can be obtained when the maximum of the filter coefficients is known. When the time delay of two received signals is formulated, the LMS algorithm can be used to get the estimate of the SINC filter coefficients, then the time delay estimate can be obtained. Compared with the traditional parabolic fitting method, the SFA can get more accurate results without increasing the computation burden. Computer simulations and water tank experiments both indicate that the SFA can obtain accurate time delay estimation.

CTR (Current transfer ratio) is generally used to characterize the reliability parameters of optocoupler in engineering. However, high-speed optocoupler has a different structure from the common optocoupler, therefore its most important parameter should be propagation delay time. In addition, CTR serving as the macroscopic parameters, its changes can’t directly reflect microscopic changes of the internal defects in device. It is discovered that the number of microscopic defects in the device and the level of low-frequency noise shows a positive correlation. In terms of high-speed optocoupler, this paper proposed a method of combining propagation delay time and low-frequency noise to evaluate the storage reliability. The paper demonstrated how to design circuit to test these parameters and obtain their variations trajectory in accelerated degradation test. In this paper, 20 VO2630 devices were divided into four groups, and a accelerated test at 100°C, 125°C, 150°C and 175°C was conducted to monitor propagation delay time and other parameters related with low-frequency noise. These parameters had different degrees of degradation. This paper showed the degradation process of propagation delay time. It was found that the initial value of propagation delay time was nearly identical, but parameters related with low-frequency noise had different initial values. The larger the initial value of low frequency noise is, the faster propagation delay time will degrade. The main cause of degradation of propagation delay time is Schottky clamped transistor degradation. Finally, this paper discussed the advantages and disadvantages about utilizing conventional electrical parameters or low frequency noise to evaluate the reliability.

The purpose of this research is to design PID control on BLDC motors using 2 tuning methods, namely Cohen-Coon and Trial & Error. PID control of formula calculations with calculations in Simulink Matlab. From the simulation results shown in graphical form, the use of the PID control gives a better effect than the use of the P and PI controls. This can be seen in the comparison curve which shows the speed of the initial start process when using the PID control. In the Trial & Error method, the response value of the system to controller P is obtained, namely, rise time = 0.0151 s, settling time = 0.6 s, overshoot = 75.9%, peak time = 1.74 s, and time delay = 0.424 s. on the PI controller namely, rise time = 0.0148 s, settling time = 0.591 s, overshoot = 76.3%, peak time = 1.74 s, and time delay = 0.0416 s. on the PID controller namely, rise time = 0.0496 s, settling time = 0.55 s, overshoot = 44 %, peak time = 1.31 s, and time delay = 0.128 s. In the Cohen-Coon method, the response value of the system to controller P is obtained, namely, rise time = 0.0168 s, settling time = 0.575 s, overshoot = 73.3%, peak time = 1.71 s, and time delay = 0.0469 s. on the PI controller namely, rise time = 0.0573 s, settling time = 0.603 s, overshoot = 39.3%, peak time = 1.23 s, and time delay = 0.142 s. on the PID controller namely, rise time = 0.276 s, settling time = 0.658 s, overshoot = 2.42 %, peak time = 0.159 s, and time delay = 0.576 s. From the simulation results it is shown that the value for the Cohen-Coon tuning method is better than the Trial & Error method, perhaps because the input value for the Trial & Error method is larger.

Accurate localization in harsh indoor environments has long been a challenging problem due to the presence of multipath. Since joint direction-of-arrival (DOA) and time delay (TD) estimation has the capability to separate the line-of-sight signal from multipath signals in the TD space, it has recently become a key technique for accurate indoor localization in next-generation WiFi and 5G networks. This paper addresses the problem of joint azimuth, elevation, and TD estimation of multiple reflections of a known signal. First, we propose an efficient approximate maximum likelihood algorithm for this problem, which updates the DOA and TD parameters alternatingly. This algorithm applies to arbitrarily distributed (planar or 3-D) arrays. Then, we present the closed-form Cramer–Rao bound for joint DOA and TD estimation, based on which we provide further analysis to show the benefit of joint DOA and TD estimation over DOA-only estimation. Although the benefit of joint estimation has been empirically shown long ago, our analysis is the first theoretical proof of it. Finally, simulation results have been provided to demonstrate the theoretical finding and the effectiveness of the new algorithm. Matlab code for the new algorithm is available at https://github.com/FWen/JADE.git .