Logical effort model extension to propagation delay representation

The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0degC to 125degC, and increases 2X while supply voltage decreasing from 1 V to 0.5 V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> t+b <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> )V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> +C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.

In this paper analytical expressions are derived for effective load capacitances of RLC interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the RC based approaches but can accommodate inductance. These new expressions are derived based on a generalized driving point admittance. The generalized driving point admittance takes inductance into consideration and hence accounts for the inductive shielding that in some cases can even exceed the resistive shielding in current technologies. Another improvement in the new effective capacitance calculation method is the utilization of a more general waveform shape that accounts for the non-monotonic behavior due to inductance effects. It is shown throughout the paper that two effective capacitances are required for accurate estimation of the propagation delay and rise time with an RLC interconnect load. Simulation results show that the error in propagation delays and rise times when neglecting inductance can be over 60% as compared to an RLC model in realistic interconnects. On the other hand, simulations show that the propagation delay and rise time maximum errors associated with the proposed approach are less than 10% as compared to SPICE.

Modern electronic systems increasingly operate across multiple voltage domains, necessitating robust and efficient level shifter (LS) circuits to ensure reliable inter-domain communication. In low-power digital applications, minimizing propagation delay and transition time is critical for achieving high-speed and energy-efficient operation. This work presents a high-performance level shifter optimized for integration within Li-ion battery charger systems. The proposed design achieves a substantial reduction in propagation delays from 0.15 to 0.09062 ns while preserving signal integrity. When integrated with a gate driver, the overall structure exhibits a propagation delay of 0.20468 ns and a transition time of 0.014 ns, marking a significant improvement from the previous 0.036 ns. Furthermore, the proposed circuit occupies only 0.00039 mm² of silicon area, representing a 92% reduction compared to prior implementations (0.05 mm²). The complete design was implemented using Taiwan semiconductor manufacturing company (TSMC) 130 nm complementary metal–oxide– semiconductor (CMOS) technology, with both schematic simulation and layout carried out in the Cadence Virtuoso design environment. These results underscore the potential of the proposed solution for compact and high-efficiency system-on-chip (SoC) battery management applications.

&lt;div class="htmlview paragraph"&gt;Transceiver propagation (also known as wrap-around, loop-back, or round-trip) delay time and output voltage slew rates have a profound impact upon bit timing. Excessive propagation delay produces an error in the generated symbol time that may cause a bit timing error in a receiving node. Any difference between the compensation time of the protocol handler and the transceiver propagation delay will be seen in the transmitted pulse time. The larger the gap, the longer the transmitted bit time. The bit distortion increases even further if the receiving node is operating in a ground offset voltage with respect to the transmitter. Bit distortion is exacerbated as well when the output voltage slew rates are too slow. When the slew rates are too slow, the receiving bit time may be too short in a positive ground offset voltage condition and too long in a negative ground offset voltage condition. Either of these issues may also contribute to the inability of the protocol handler to successfully arbitrate the bus. The transmitting node may diagnose a short-to-ground condition and cause glitches on the bus.&lt;/div&gt; &lt;div class="htmlview paragraph"&gt;Transceiver propagation delay must be designed to be compatible with the compensation capabilities of the intended protocol handler(s). Output voltage slew rates must also be understood so that the total contribution of these two errors does not result in the inability to transmit successfully into maximum ground offset conditions.&lt;/div&gt;

The unified logical effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic gates and resistive wires is presented. The method provides conditions for timing optimization while overcoming the limitations of standard logical effort (LE) in the presence of interconnects. The condition for optimal gate sizing in a logic path with long wires is also presented. This condition is achieved when the delay component due to the gate input capacitance is equal to the delay component due to the effective output resistance of the gate. The ULE delay model unifies the problems of gate sizing and repeater insertion: In the case of negligible interconnect, the ULE method converges to standard LE optimization, yielding tapered gate sizes. In the case of long wires, the solution converges toward uniform sizing of gates and repeaters. The technique is applied to various types of logic paths to demonstrate the influence of wire length, gate type, and technology.

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

The role of network structure and time delay in a metapopulation Wilson--Cowan model

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. Essentially, the propagation delay is shown to be the sum of the step-response delay and an input dependent delay that may account for as much as 50-100 percent of the total delay. The matching between the ramp input and the characteristic input waveforms is shown to be easily performed for excellent agreement in output response and propagation delay. Even though the short-circuit current is neglected, its influence is shown to be small and may be corrected. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.

This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a post-processing step, wire width optimization under an accurate higher-order delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.

A new analytical delay model for high-speed CML circuits is presented. It is applicable to high-speed/low-voltage-swing silicon and HBT CML circuits operating at medium or high current densities. The model is based on bipolar SPICE parameters file, and can be used to estimate the propagation delay time of CML circuits under different operating conditions. The detailed transient analysis accounts for delay components due to each element in the complete SPICE bipolar transistor model. The comparison to SPICE circuit simulation results show excellent agreement for a wide range of state-of-the-art technologies and circuit parameters. The new model predicts the delay time with less than 5% error in most cases. The influence of the finite slopes (slewing rate) of the input signal and the device dimensions is also investigated. The delay model determined the optimum current i/sub 0/ (or load resistor R/sub L/) for a transistor of a certain emitter area when driven by a source of a voltage swing (/spl Delta/V) and slew time (t/sub r/). At a specified power dissipation, the delay model is used to optimally size the transistor emitter area for maximum switching speed. The model provides circuit and device guidelines to minimize the propagation delay time and improve the performance of high-speed CML circuits. >

A high-performance 4-bit carry lookahead generator macrocell integrated circuit similar to the commercial 2902, a member of the 2900-family microprocessor chip set, was designed and built using direct-coupled FET logic (DCFL) and buffered FET logic (BFL) GaAs technologies. The following propagation delay times and power dissipations were measured: DCFL version -T/SUB pd/=1.55 ns, P=34 mW; BFL version-T/SUB pd/=1.10 ns, P=520 mW. In contrast, the commercially available bipolar 2902 has a propagation delay (room temperature typical) of 4.5 ns with an average power dissipation of 260 mW.

This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. The method is based on the logical effort delay model. The minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The analytical formulation of the method takes into account the maximum input capacitance, the load to be driven, and the given timing constraint. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents small average errors of 1.48% in power dissipation, 2.28% in delay propagation, and 6.5% in transistor sizes.

Triangular carbon nanotube (T-CNT) bundles are proposed as long interconnects for subthreshold VLSI circuits. The performance of subthreshold interconnects depends on the intrinsic quantum and electrostatic coupling capacitances of the interconnects. Proposed T-CNT bundles have the most optimum geometry that give least possible coupling capacitance between adjacent wires in an IC. First, we describe the T-CNT bundle models and of traditionally used square/rectangular CNT bundles for comparison. The subthreshold output current of an inverter is modelled, and hence, we find the optimum transistor widths for nFET and pFET that drives the subthreshold interconnects. This is carried out by the current-over-capacitance ratio approach, where the subthreshold current and the transistor output capacitance are considered. Then, we model the interconnects using equivalent single conductor models and find their propagation delay and power dissipated. The performance factors such as crosstalk-induced delay, power delay product and victim noise levels of capacitive coupled interconnects of T-CNT bundles are compared to traditionally used square/rectangular CNT bundles for lengths ranging from 500 μm to 2000 μm. We find that T-CNT bundles outperform square/rectangular CNT bundles.

The purpose of this paper is to sum up concerns when designing a gate driver for SiC MOSFETs, and provide two examples. Both of them can detect over current of the power device. One use a gate driver IC and adapt it to meet the requirement of SiC MOSFETs, which is simple and convenient. For better performance in terms of switching frequency and reliability, the other one adopt magnetic transformers to provide the gate signals and the power for the secondary side respectively. The gate driver can work on any duty ratio and meet fast dynamic duty ratio command. A second order R-C network is designed to detect over current of the power device. Experimental comparison shows the latter performs better on propagation delay and coupling capacitance. At last short circuit experiment is conducted and both can survive the experiment.

The work focuses on the impact of the finite and variable MOSFET output resistance on the transient response LC transmission line drivers. Experimental results highlight the severe error occurring in conventional timing analysis when actual finite resistance of the device is neglected. A novel analytical model is presented to capture the variable resistance of the driver. The model allows closed‐form expressions for the output waveform to be carried out, and it agrees well with HSPICE simulations. The proposed model is suitable to figure fundamental timing parameters of CMOS gates driving lossless transmission lines, such as the propagation delay, transition time, as well as power estimation. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 1504–1509, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22496