CMOS Based Voltage Reference Designs for Sub - 1V

Trimming process and temperature variation in second-order bandgap voltage reference circuits

A CMOS process-insensitive voltage reference generator, which is based on the weighted sum of thermal voltage and difference of threshold voltages, is presented. The voltage reference circuit uses high VTH and regular VTH transistors and produces reference level of 422mV. The proposed technique is analyzed theoretically and its results are compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology for low-cost low-power applications. The circuit operates at minimum supply voltage of 1V with maximum drawn current of 577nA only. A temperature coefficient of 36ppm/°C is achieved with line sensitivity of 0.01%/V. The proposed reference generator exhibits PSRR of -60.34 dB and -37.09 dB at 100Hz and 1MHz, respectively.

The electromyographic (EMG) activity of shoulder and forearm muscles was recorded during a standardized computer task with different combinations of time pressure, precision demands, and mental demands to study the interaction of these factors and their effect on muscular response during simulated computer work. The computer task lasted 5 minutes, and it was performed by 14 female computer-aided design (CAD) operators during 8 exposure combinations that differed with respect to time pressure, precision demand, and mental demand. Performance (number of produced drawings, mouse clicks, and errors) were recorded. The EMG activity was recorded from the trapezius, infraspinatus, deltoid, and extensor digitorum muscles. An electrogoniometer was used to measure wrist postures and movements. High time pressure (combined with low precision and low mental demands) resulted in higher EMG activity for all the muscles and in a small increase in the number of produced drawings. High precision demands caused a large reduction in the number of produced drawings, but not always a change in EMG activity. High precision demands and high mental demands led to no change or a reduction in muscle activity because the number of drawings was greatly reduced. The interaction between work pace and other exposure factors must be taken into account when the effects of changes in exposure demands on muscular response are predicted. Only then can it be predicted whether changing demands will constitute a risk of developing musculoskeletal disorders.

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

To improve the performance of typical first-order bandgap references, a high precision bandgap voltage reference with second-order curvature correction is proposed in this paper. Utilizing a temperature independent current (has nothing to do with the temperature of first order) and a proportional to absolute temperature (PTAT) current, a proportional to the square of temperature (PTAT2) current can be generated, which can be further used to compensate the second-order term in the Taylor-series expansion of the diode voltage, and the precision of the voltage reference is improved. The design was verified in a Bi-CMOS process, and simulation results showed that the temperature of the designed voltage reference was 10 ppm/°C at the temperature range from −45°C to 125°C and the consumed current was 7 µA at 5V supply voltage.

Chapter 1 - Voltage References and Voltage Regulators

A 28 ppm/°C, 2.54 ppm/V, −77 dB@100 Hz pico-ampere voltage reference for high-end IoT systems

Wireless Sensor Network (WSN) is one of the supporting technologies for the Internet of Things (IoT). However, a large-scale deployment of the WSN faces multifarious challenges. WSN node size and maintenance cost incurred by periodic energy source replacement are among them. From the perspectives of energy sources, these two challenges can be better addressed by Wireless Power Transfer (WPT) technologies in comparison with energy-scavengers or traditional energy-storages. Omnidirectional-Electro-Magnetic (EM)-Radiation WPT-technology appears to be a viable choice. Hence, this work proposes various circuit design techniques in developing the dedicated Power Management Integrated Circuit (PMIC) structures to facilitate implementation of such WPT technology. In detail, this thesis describes (i) a sub-1-V CMOS Voltage Reference (VR) with novel trimming networks, (ii) a Capacitor-Less (OCL) Low Drop-Out Voltage Regulator (LDO) with load-adaptive negative-resistance at the input stage of an Operational Transconductance Amplifier (OTA), and (iii) a compensator-less Square Root Voltage Mode (SRVM) controller for a Pulse Width Modulation (PWM) Discontinuous Current Mode (DCM) Boost DC-DC Converter. To elaborate, the trimming networks aim at minimizing Temperature Coefficient (TC) against process variations and the finite resistance of the CMOS trimming switches in a CMOS Voltage Reference (VR). The loadadaptive negative-resistance helps to boost the DC-gain of the proposed OCL-LDO while improving the current efficiency and ensuring fast-settling and frequency stability. Lastly, the compensator-less SRVM controller is designed to minimize power and area from the discrete compensator circuits in conventional DC-DC converters. Subsequently, structures of three key PMIC building blocks, such as a VR, an OCL-LDO and a boost DC-DC switching converter, are proposed with the aforementioned circuit design techniques. Trimming networks are proposed for a sub-1-volt CMOS VR implemented using the threshold-voltage-difference (Vth) approach. Fabricated in 0.18-m CMOS-technology, the trimmed CMOS VR consumes 0.4 A with a supply voltage of 0.7 V. A TC of 45 ppm/C and a xi Power Supply Rejection (PSR) greater than -55 dB up to 10 MHz. The trimmed VR can also operate under supply voltages from 0.7 V to 1.5 V and operating temperature range from -40 C to 80 C. A fast-settling OCL-LDO enhanced by a load-adaptive negativeresistance is proposed. Such load-adaptive negative-resistance resides at the EA input-stage, which incorporates a Partial-Positive-Feedback (PPF). No compensation capacitors is needed for frequency stability as a result. The overall OCL-LDO is manufactured in 0.18-m CMOS-technology. It achieves a fast settling-time of 2.99 s and 2.05 s against a load step-up and -down respectively between 30 mA and 80 mA in 100 ns. The OCL LDO functions under supply voltages from 0.8 V to 1.5V. It consumes quiescent current of no more than 21 A under no-load condition; it can source as much as 80 mA to the loading ICs.

Welcome to the 14th ACM/IEEE International Symposium on Low Power Electronics and Design! The 2009 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to San Francisco, the liberal fog-city of million rainbows by the bay in California, USA. On a par with this great location, a strong and diverse technical program features four exciting keynote talks from leaders in the field, two plenary special sessions in line with our symposium theme on Green Data Centers and Computing, a technical panel on SoC Power management, and four informative half-day embedded tutorials scheduled for the last day of the symposium. New for this year's ISLPED has been identified as the symposium theme with an array of invited keynote speeches, special sessions and tutorials covering this theme. Dr. Percy Gilbert, VP of Technology Development at IBM, will give a keynote on advances in process technology and IBM collaborative ecosystem for leadership power performance SOC designs on Wednesday. The Thursday keynote will be delivered by Dr. Kevin Zhang, director of advanced design and Intel Fellow, who will discuss the opportunities and challenges of circuit design in Nano-Scale CMOS era. We will have two keynote speeches on Friday by Dr. Mojy Chian, the senior VP of the newly formed Global Foundries and by Dr. Yankin Tanurhan, VP of engineering and design at VirageLogic. Dr. Mojy Chian and Dr. Yankin Tanurhan will give talks on the challenges of low-power design enablement for foundry technology offerings and various opportunities in the semiconductor industry for the IP suppliers. These keynotes talks cover the topic from foundry technology to IP design and will be interesting to see the speakers' perspectives on what are the demands of IP design from advanced technologies. New for ISLPED 2009 is the introduction of a theme. This year's theme focuses on green computing toward which special sessions and tutorials are lined up. On Wednesday, we have a two-hour special session on data centers including data centers power management, integrated compute and packaging solutions, and more by Prof. Massoud Pedram, University of Southern California, Prof. Tom Wenisch, University of Michigan, Cullen Bash, principal scientist and research manager at Hewlett Packard Labs, and John Carter, manager of power-aware systems at IBM Austin Research Laboratory. The Thursday special session welcomes three speakers, Dr. Kiyoo Itoh, fellow of Hitach, Al Fazio, fellow and director of Memory Technology Development at Intel, and Prof. Suman Datta form Pennsylvania State University covering topics including low power and future non-volatile memories, low voltage circuits and transistors. On Thursday, a panel is scheduled on SoC Power Management and its controversial topics. This panel will be moderated by Brian Fuller who is an editor and consultant. We have four panelists including Sandeep Mirchandani from Broadcom, Sanjeev Das from NXP, Ran Avinun from Cadence, and Camille Kokozaki of IDT. The four embedded tutorials on Friday are organized around major themes of (1) semiconductor technologies for computing, and (2) system design issues with emerging technologies. Prof. Kaushik Roy of Purdue University will introduce ultra low voltage CMOS. Prof. Suman Datta of Pennsylvania State University and Prof. Vijay Narayanan of Pennsylvania State University will cover transistors to architectures. Prof. Vijay Raghunathan of Purdue University will introduce the topic of self-powered embedded systems and Dr. Norm Jouppi, fellow of HP Labs and Prof. Yuan Xie of Pennsylvania State University will discuss emerging technologies and their impact on system design. We have a very exciting technical program in ISLPED 2009. Out of 208 paper submissions that we received, 72 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 25% for regular and short papers (52 papers), or 35% including the additional 20 posters. Topics range from low power technology, circuits, and memory; low voltage analog and RF design; power aware design and tools; power efficient architecture techniques; and system and application level power optimization. The program is organized into eleven technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as one interactive poster session that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition ISLPED includes industry sessions and exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. Winning entries to the annual Student Low Power Design Contest will also be featured in a separate technical session in ISLPED.

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18[Formula: see text][Formula: see text]m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7[Formula: see text]V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47[Formula: see text]nW, at a supply of 0.7[Formula: see text]V. A temperature coefficient (TC) of 42[Formula: see text]ppm/[Formula: see text]C is achieved when the temperature ranges from [Formula: see text]20[Formula: see text]C to 80[Formula: see text]C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

Two sub-1-V MOSFETs only voltage reference designs, working in subthreshold region are proposed. They consume ultra-low power, exhibit high temperature and supply voltage independence, operate at sub-1-V supply and are suitable for fabrication using N-well CMOS technology. A voltage reference circuit (circuit-1) with dual-threshold voltage MOSFETs, which can provide a nominal output voltage of 554 mV exhibiting high temperature-compensation is proposed. Simulation results show that it has a temperature coeffcient of $$13\,\hbox {ppm}/^{\circ }\hbox {C}$$ and a power consumption of 2.1 nW. Another reference circuit (circuit-2) using only single threshold voltage MOSFETs with a high nominal output of 773 mV is also proposed. Simulation results show that it has a line sensitivity of 0.073%/V and a power consumption of 2.4 nW. Statistical analysis based on Monte-Carlo simulation show that the performance of both the circuits will not be significantly affected by process variations.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

A novel voltage reference based on depletion device was developed with combination of depleted NMOS voltage reference and current reference independent to VDD. The circuit was designed with TSMC-0.25 mum mixed-signal process, and simulated by Spectre. The results indicated that TC is only 33 ppm/degC and PSRR can reach 62 dB at 10 KHz.

A formalized technique for the automated design of bandgap voltage reference (BVR) is proposed. The distinctive feature of the technique is the automation of the synthesis of the circuit engineering conceptions by the given parameters of the source, which considerably reduces the design time. Based on the developed technique by the 180-nm SOI technology, the circuit of the voltage reference source was designed. The obtained schematic solution has the following desired characteristics: the power supply suppression ratio at the frequencies of 1 kHz in the worst case is –60 dB and at the frequencies of 1 MHz is –44 dB, the maximum consumption current is 25 μA, the temperature coefficient is 24 ppm/°C in the temperature range from –70 to 150°C, and the ratio of changing the output voltage to changing the supply voltage is 354 μV/V in the range of supply voltage from 2.4 to 7 V.

Comparator plays a very important role in most of the analog circuits like ADC and DAC and the performance of these analog circuits is majorly influenced by the choice of the comparator. A low power and high speed comparator is required for high speed Analog to digital converter. In this paper a well defined and improved design of CMOS comparator is presented which is suitable for Ultra Low power Sigma to Delta Converter. The comparator design is a modified design of two stage CMOS op-amp. The proposed comparator is realized using Cadence Virtuoso. Design and Simulation are carried using 180nm CMOS process technology and 1.8 power supply. Input voltage and reference voltage are taken as 1V and OV respectively for comparison. The results of the proposed comparator are compared with the earlier work done [1], [3], [4] and hence we can clearly see the improvement in power dissipation of the proposed comparator. With the proposed comparator design we achieve ultra low power consumption of 21.16uW.