CMOS Compatible Electroless Plating Process for Under Bump Metallization

Solder joint reliability is dependent on both thickness and morphology of the intermetallics that form and grow at the solder joint interface during soldering and subsequent thermal ageing and examining the morphology of these intermetallics is of great importance. The focus of this paper is to present experimental results of a comprehensive study of the interfacial reactions during soldering of Sn-Ag-Cu lead-free solders on copper (Cu), immersion silver (ImAg), electroless nickel/ immersion gold (ENIG) and electroless nickel/ electroless palladium/ immersion gold (ENEPIG) surface finishes. Using scanning electron microscopy detailed a study of the 3-D morphology and grain size of the intermetallics was conducted. The results showed that when soldering on ENIG and ENEPIG finishes several morphologies of intermetallics with different grain sizes form at the solder joint interface compared to a single intermetallic morphology that forms when soldering on copper and immersion silver. An attempt was made to discuss the effect of several factors that may have an influence on the type of morphology the intermetallics may grow into. The results obtained in the present investigation also revealed that the technique of removing the solder by deep etching to examine the morphology of intermetallics is a convenient and efficient method to investigate the intermetallics formed at the solder joints.

In our experiment, the possibility of forming copper wire bonds in Chip-on-Board (COB) applications was investigated. In the experiment, such surface finishes were studied and compared which are common in printed circuit board based COB applications and can be bonded with wire bonding technologies. These finishes were immersion silver (ImAg), electroless nickel / immersion gold (ENIG) and electroless nickel / electroless palladium / immersion gold (ENEPIG). On each type of surface finish, copper wires with two diameters (33 and 300 μm) were bonded with a TPT Ultrasonic bonder. The wire bonds then characterized by optical inspections and mechanical measurements which are detailed in the paper.

High-throughput assembly technologies to form Copper (Cu) interconnections without solders at below 200°C, and pitch below 40µm has been a major challenge in the semiconductor industry. A unique solution has been demonstrated by Georgia Institute of Technology to overcome this grand challenge. This technology utilizes thermocompression bonding to form copper interconnections with process tolerances to accommodate non-coplanarities of bumps and warpage of the substrate, without solders. The bonding pressure applied for thermocompression was 365MPa, to enable Cu bump collapse by 3µm. As thermocompression bonders are generally force-limited to 400N, such high bonding pressures may hinder scalability of this technology to fine pitches with higher I/O densities. This paper addresses this manufacturability challenge with the novel Electroless Palladium Autocatalytic Gold (EPAG) surface finish instead of the standard Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) finish, previously used to prevent Cu oxidation for bonding load reduction down to 120MPa.

Electroless nickel (Ni) electroless palladium (Pd) immersion gold (Au) (ENEPIG) substrate metal finish was evaluated for suitability for handheld product. 3 main focus areas were covered in the evaluation: plating thickness measurement system, processibility and reliability. The plating thickness measurement system was established with physical analysis and mirco X-ray fluorescence. The processibility studies included Au-wire bondability on ENEPIG bond finger and lead free (Pb-free) solder paste printing on solder pad. The result showed feasibility of manufacturing electronic packages using ENEPIG substrate could be obtained with certain level of process parameters optimization. Package level reliability showed ENEPIG substrate had comparable reliability performance compared to Electrolytic NiAu / CuOSP substrate. For board level reliability, the temperature cycling on board (TCoB) and bend test (BT) showed ENEPIG substrate performed similarly but drop test (DT) showed earlier first drop to failures. The low package standoff offered acceptable number in first drop to failure despite of the application of ENEPIG substrate. Difference in substrate outer Cu layer thickness was discussed as a factor influencing drop test performance. Failure analysis (FA) found different drop testing failure modes over the ENEPIG substrate samples and CuOSP substrate samples.

An electroless nickel (Ni)/electroless palladium (Pd)/immersion gold (Au) (ENEPIG) surface finish is widely applied to substrates used in various semiconductor packages. However, many issues have been arising in terms of solder joint reliability (SJR) during the assembly process. A number of factors can affect SJR such as thickness of each layer of ENEPIG, reflow profile, plating bath conditions, chemical composition of Pd and Ni layer, and chemical composition of solder balls. This paper focuses on investigating the influence of the factors on SJR and formation of intermetallic compounds (IMCs). The present study investigated the effect of the number of reflows (1, 3 and 5), Ni and Pd thickness of ENEPIG (Ni: 3, 6 and 9 µm, Pd: 0.02, 0.06 and 0.1 µm), chemical composition of Pd layer (pure Pd and Pd-phosphorus (P)) and chemical composition of solder balls (tin (Sn)0.7copper (Cu), SAC305 (Sn3.0 silver (Ag) 0.5Cu), SAC302 (Sn3.0Ag0.2Cu) and Sn3.5Ag). Special focus involved the combination of solder balls (SAC305 and Sn3.5 Ag) and chemical composition of the Pd layer (pure Pd and Pd-P). SJR that were evaluated through pull test and shear test, and then IMCs were observed through scanning electron microscope (SEM) analysis. The effect of Pd and Ni thickness with Pd-P and pure Pd was confirmed. Compared to Pd-P ENEPIG, a relatively high risk of SJR was found when using solder ball with no or low Cu content (e.g., SAC302 and Sn3.5Ag) and pure Pd ENEPIG. As a result of SEM analysis, Kirkendall voids were observed in the Ni <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> SnP IMC layer only on pure Pd ENEPIG with Sn3.5Ag solder balls and the fracture occurred along the void line. For Sn3.5Ag, a thicker P-rich layer (around 700 µm) was formed compared to SAC305 (300µm).

Many integrated circuits (ICs) will operate well above their maximum rated temperature of +70°C or +125°C, but are often not packaged appropriately to reliably endure temperatures above +150C. Specifically, the original gold or copper bonds on the aluminum die bond pads are prone to Kirkendall or Horsting voiding, particularly at temperatures greater than +150°C. Also the mold compounds used in plastic packaging for IC assembly can degrade at these elevated temperatures. In some cases, commercial demand for higher temperature reliability can justify a separate offering of ICs assembled in hermetic, ceramic packages from the original component manufacturer (OCM). However, in most cases, the market demand is deemed insufficient. Global Circuit Innovations (GCI) has developed a high-yielding process, which can remove a semiconductor die (i.e., computer chip) from a plastic package, remove the original bond wires and/or ball bonds, plate the aluminum die bond pads with Electroless Nickel, Electroless Palladium, and Immersion Gold (ENEPIG), and then reassemble the now improved semiconductor die into a hermetic, ceramic package. Device Extraction, ENEPIG die bond pad plating and Repackaging (DEER) provides an improved die bond pad surface such that works well with either gold or aluminum bond wires in applications up to +250°C without mechanical or electrical connectivity degradation. GCI routinely exposes sample devices to +250°C bakes with 100% post bake yields so as to continuously ensure that any device processed with the DEER technology will reliably perform in high-temperature environments. Although the oil and gas industry has already expressed significant interest in the DEER process, with excellent lifetest and production application results demonstrating dramatically increased component lifetimes at elevated temperatures, this technology can also be leveraged for any application exposing ICs to harsh environments. Not only is the high-temperature reliability dramatically increased, but also the new hermetic, ceramic package protects the IC from a variety of elements and environments (i.e., corrosives and moisture).

Interactions and dispersion stability of aluminum oxide colloidal particles in electroless nickel solutions in the presence of comb polyelectrolytes

Interconnecting to aluminum- and copper-based semiconductors (electroless-nickel/gold for solder bumping and wire bonding)

This study investigates the application of electroless nickel deposition on additively manufactured stainless steel samples. Current additive manufacturing (AM) technologies produce metal components with a rough surface. Rough surfaces generally exhibit fatigue characteristics, increasing the probability of initiating a crack or fracture to the printed part. For this reason, the direct use of as-produced parts in a finished product cannot be actualized, which presents a challenge. Post-processing of the AM parts is therefore required to smoothen the surface. This study analyzes chempolish (CP) and electropolish (EP) surface finishing techniques for post-processing AM stainless steel components CP has a great advantage in creating uniform, smooth surfaces regardless of size or part geometry EP creates an extremely smooth surface, which reduces the surface roughness to the sub-micrometer level. In this study, we also investigate nickel deposition on EP, CP, and as-built AM components using electroless nickel solutions. Electroless nickel plating is a method of alloy treatment designed to increase manufactured component’s hardness and surface resistance to the unrelenting environment. The electroless nickel plating process is more straightforward than its counterpart electroplating. We use low-phosphorus (2–5% P), medium-phosphorus (6–9% P), and high-phosphorus (10–13% P). These Ni deposition experiments were optimized using the L9 Taguchi design of experiments (TDOE), which compromises the prosperous content in the solution, surface finish, plane of the geometry, and bath temperature. The pre- and post-processed surface of the AM parts was characterized by KEYENCE Digital MicroscopeVHX-7000 and Phenom XL Desktop SEM. The experimental results show that electroless nickel deposition produces uniform Ni coating on the additively manufactured components up to 20 μm per hour. Mechanical properties of as-built and Ni coated AM samples were analyzed by applying a standard 10 N scratch test. Nickel coated AM samples were up to two times scratch resistant compared to the as-built samples. This study suggests electroless nickel plating is a robust viable option for surface hardening and finishing AM components for various applications and operating conditions.

In this study, we used copper (Cu) posts, plated to a height of 150 μm, as interconnections to form electrodes between different package layers. The upper layer consisted of a chip-scale package (CSP), while the lower layer was made up of a flip chip-chip scale package (FCCSP). We plated a Cu post on the side of FCCSP substrate, and produced the FCCSP package by thermo-compression (TC) bonding with copper pillar solder bumps on the center of substrate. The surface of the bottom electrode for the upper CSP received a surface finish of electroless nickel, electroless palladium, and immersion gold (ENEPIG). The bonding surface of the lower FCCSP was the bare Cu surface of the epoxy-molded Cu post. The PoP joining process used a vacuum reflow process with solder paste and solder balls. To understand the package joint's characteristics, we measured voids and shear strength, and analyzed the cross-sectional microstructure. The temperature profile used in the PoP joining process demonstrated optimal joint characteristics with a joint void content of 2.3% and a joint strength of approximately 44 MPa when formic acid was utilized and the activation preheating time was extended. Cross-sectional warpage analysis of the PoP package revealed a minimal difference of approximately 31 μm between the center and the ends. This study successfully developed a stacked package with a PoP structure using Cu Post, and the bonding process was optimized to minimize warpage in the PoP package.

The technology of surface finishes for printed circuit boards is seeing a dramatic shift from the Hot Air Solder Levelling (HASL) towards alternative finishes like electroless Nickel - immersion gold (ENIG), immersion tin, immersion silver and organic solder preservatives (OSP's). This trend is mainly caused by the worldwide environmental pressure to ban the use of lead for electronic assemblies as well as the demands of modern assembly technology, which require a higher coplanarity of the surface finish for surface mount assembly. One of the main benefits of HASL is the extremely good resistance of the surface against ageing under high temperature conditions. Alternative finishes, due to their limited thickness, offer excellent coplanarity, but inferior surface protection. A detailed understanding of the ageing processes is thus a prerequisite for the implementation of alternative surface finishes in high yield PCB production. In this paper the ageing characteristics of immersion tin surface finishes are investigated and correlated with the reliability during soldering operations. Ageing of tin surface finishes takes place by intermetallic compound (IMC) formation at the Sn/Cu interface due to solid state diffusion. Hence the kinetics of the process is assumed to follow a simple law. The kinetics of IMC formation was investigated experimentally and correlated with data from literature. The results show that the simple kinetic model leads to an overestimation of the kinetics in the temperature regime below 60°C. Changes in the reaction mechanism with temperature as well as with time must be taken into account for a conclusive understanding of the ageing characteristics. The only parameter with relevance for practical solderability is the thickness of the immersion tin layer.

A comparative study of two techniques to depth profile multilayer NiFe alloy coatings has been performed. Both conventional cross-sectioning with energy-dispersive x-ray imaging (EDX) and glow discharge optical emission spectroscopy (GDOES) sputter depth profiling methods have been compared in terms of analytical accuracy, spatial resolution, ease of use and ultimately overall cost. The advantages and disadvantages of each technique have been highlighted, and while both methods exhibit good compositional agreement, the GDOES technique offers great advantages in turn-around time due to the minimal sample preparation required. Additionally, where the overall coating is thin or individual layers are thin, then the spatial resolution of GDOES is much better than that of EDX. An objective definition for GDOES spatial resolution has been created based on the optimum resolution obtainable and represents the overall resolution minus the degradation due to crater shape. This is shown to be a factor of approximately four times better than the true spatial resolution, but nonetheless presents a useful baseline guide to what is actually observed. © 1997 by John Wiley & Sons, Ltd.

Limitations of Nickel Hypophosphite Electroless Nickel Processes

The use of surfactants and supercritical CO2 assisted processes in the electroless nickel plating of printed circuit board with blind via

Glow discharge optical emission spectroscopy (GDOES) is an analytical technique that provides both a surface and depth profile of the elemental composition and distribution of solid or porous samples. Although GDOES is a destructive technique, it provides the advantage of being a high throughput technique that is highly sensitive to all elements from H to U and can provide high resolution (from nm to µm) depth profiles of elemental distributions in practically any sample. Previous works have investigated and optimized the operating parameters of using GDOES to study negative electrode materials and from the data gathered therein [1] we used 5% H2 in Ar gas in this study to increase sputtering rate of Li-NMC cathode materials and to increase sensitivity to Li in the sample to provide a more detailed elemental distribution. This study investigates the use of GDOES as a method for analyzing elemental and specifically lithium distribution in Li-NMC cathode materials in extreme depth and with validation from other techniques such as x-ray photoelectron spectroscopy (XPS) and x-ray fluorescence (XRF) and with additional morphological analysis of cells using x-ray computed tomography (X-ray CT).In this study coin cells were assembled in an Ar filled glovebox using a 15 mm diameter double sided graphite anode coated on a Cu current collector, 14 mm double sided NMC 111 cathode coated on an Al current collector, either a Celgard 3401 or 5550 separator, and 75 µL of 1M LiPF6–EC:EMC (3:7) electrolyte. The coin cells were then brought outside and EIS data was taken on the freshly made cells. They were then allowed to rest for 12 hours before going through a formation cycle at a C-rate of C/20. After the formation cycle, all cells went through 10 charge/discharge cycles at a C-rate of C/5. After these cycles EIS data was taken again and the cells were then charged to different states of charge (SOC) of 0, 25, 75, and 100% and again EIS data was taken after this. The cells were then brought back into the glovebox where they were de-crimped and disassembled. The electrodes were then rinsed in DMC and dried. They were then analyzed using XPS for surface analysis, XRF for elemental mapping, and X-ray CT for analysis of electrode morphology. Finally, they were analyzed using GDOES and the through thickness Li atomic distribution was plotted for the SOCs listed. An example of atomic concentration distribution of various elements for a SOC of 0% is shown by Figure 1. This study aims to validate the use of GDOES to generate accurate Li distribution profiles and elemental distributions in Li-NMC cathode materials.[1] H. Takahara, A. Kojyo, K. Kodama, T. Nakamura, K. Shono, Y. Kobayashi, M. Shikano, and H. Kobayashi, J. Anal. At. Spectrom., 29, 95–104 (2014). Figure 1