CNTFET for Logic Gates Design

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

Due to extraordinary physical and electrical properties, carbon nanotubes have become one of the most promising technologies that might someday pick up where conventional CMOS devices leave off. This paper details analysis of power and delay performance of carbon nanotube field effect transistor- based universal logic gates (NAND and NOR gates). Though electrolyte-gated carbon nanotube field effect transistor have exhibited the highest performance than top-gated and back-gated carbon nanotube field effect transistor, the work demonstrates that energy delay product and switching time performance of 30nm channel length top-gated carbon nanotube field effect transistor - based NAND gate is much better than 20nm channel length electrolyte-gated carbon nanotube field effect transistor technology. As the performance of p type carbon nanotube field effect transistor is better than n type carbon nanotube field effect transistor, 30nm channel length top-gated carbon nanotube field effect transistor-based NOR gate is 4% faster than corresponding NAND gate and its energy delay product is 46% lesser than that of NAND gate.

This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

In this paper it is proposed the implementation in Matlab & Tools environment, by using Simulink and Simscape plug-ins, of empirical models of the Carbon Nanotube Field Effect Transistor (CNTFET) in order to evaluate the capability of this very interesting design and simulation environment to easily design the most advanced generation of digital electronic circuits. Empirical models of electronic devices are particularly suitable for the Computer Aided Design (CAD) of digital electronic circuits. They are generally very compact, fast and accurate, without any physical approximation, and then they can be easily implemented in circuit simulators. The paper aims at describing the core of a possible CAD tool for digital circuits using CNTFETs, designed by the author, and at evaluating its suitability and usefulness by design examples. Therefore, they have been implemented two models of CNTFETs in Matlab & Tools environment and it has been performed the design of basic digital logic gates and memory elements. One of the two models has been developed by the author and already validated. The other model has been developed by valuable authors at Standford University and is used for comparisons. Results show the great usefulness of the empirical approach and of the Matlab & Tools environment for the quick and easy design of digital electronic circuits using CNTFETs.

This paper proposes an energy efficient Carbon Nanotube Field Effect Transistor (CNFET) based architecture of 4-input Look-up Table (LUT), a building block of Field programmable gate arrays. HSPICE simulation based on Berkeley Predictive Technology Model (BPTM) for 32 nm channel length device shows that for Iso-area, the CNFET based LUT is 98% more leakage power efficient than the LUT implemented in the bulk CMOS. Similarly, at operating frequency of 250 MHz and at supply voltage of 0.9 V compared to bulk CMOS LUT, the proposed Hybrid LUT and CNFET LUT provides 36% and 53% improvement in power delay product respectively.

In this work, we have presented the design of voltage level shifter using carbon nanotube field effect transistors (CNTFETs). The proposed design is capable of converting two input voltage levels to two output voltage levels. The threshold voltage of CNTFETs is suitably chosen to achieve the desired output. The proposed design can perform both up and down shifting which is very useful in the system-on-a-chip design to interface with other peripherals. It exhibits lower delay and power delay product in comparison with the existing complementary metal–oxide–semiconductor-based voltage level shifters. The proposed circuit is very effective as it eliminates the requirement of additional voltage level shifter for designing systems with multi-power supply voltage domain in the nanoscale regime. The design has been analyzed for different process, voltage and temperature corners. It has been shown that the design works perfectly with [Formula: see text] variation in the diameter of the carbon nanotubes used in the CNTFET. The performance varies slightly with [Formula: see text] variation in operating voltage. Our analysis shows that the design is thermally stable for a wide variation in operating temperature.

On the design of robust, low power with high noise immunity quaternary circuits

An ultra-low power 8-Transistor Modified Gate Diffusion Input (MGDI) Carbon Nano Tube Field Effect Transistor (CNTFET) Full Adder (FA) has been presented in this paper. The proposed 8-T MGDI CNTFET Full Adder outperforms other adders in terms of Power Consumption, Propagation Delay and the PDP at different levels of Power Supply and Temperatures. The power consumption of the proposed 10 nm CNTFET 8-T MGDI Full Adder at 27°C is 1.96 nW. The proposed CNTFET FA exhibits 60.32% improvement in Power Consumption when compared to the existing 10 nm FINFET 8-T MGDI Full Adder. The propagation Delay of the proposed FA is 42.16 ps and an improvement of 57.68% is noticed over the existing FA. The Power Delay Product of the proposed 10 nm CNTFET 8-T MGDI FA is 82.63 × 10−21 Jules, whereas the PDP of the 10 nm FINFET 8-T MGDI FA is 492.07 × 10−21 Jules. The PDP of the proposed 10 nm CNTFET 8-T MGDI Full Adder exhibits 83.21% improvement when compared to the 10 nm FINFET 8-T MGDI FA.

The VLSI based circuits often pose challenges in the form of various faults (such as transient faults, permanent faults, stuck-at-faults). These faults appear even after testing also. They occur because of reduction in the size of the circuit or during realtime implementation, as these faults are difficult to detect. It is very important to detect and rectify all such faults to make the system foolproof and achieve expected functionality. In this paper, 12 transistors based, full adder circuit (12T-FAC) using Carbon Nanotube Field Effect Transistor (CNFET) technology is proposed. The proposed design based on CNFET provides high fault resistance towards transient, permanent faults and works with least power, delay and power-delay product (PDP). Later, features like fault detection and correction circuit have been added in 12T-FAC. The final version of full adder circuit capable of correcting errors has been used in designing applications like multipliers. The proposed full adder circuit was designed with CNFET technology, simulated at 32 nm with supply voltage +0.9 V using the Cadence Virtuoso CAD tool. The model used is Stanford PTM.

Ternary Logic is the best and suitable alternative for binary logic. Binary Logic consists of 2 logic states 0 and 1 whereas ternary logic contains three states logic 0, 1 and 2. The advantages of Ternary over binary logic is it improves switching speed. This technique helps to reduce the computation steps, complexity and chip area. This paper is a study of CNTFET based ternary logic gate and improved impact on power and delay. A ternary NAND, NOR Gates are designed using Carbon nanotube transistors. The TNAND and TNOR gate circuits are simulated using the HSPICE tool. The performance parameters of the TLG using Carbon Nanotube FETs in terms of Delay are 621ps, 20.66ps, in terms of power are 0.47μW, 0.53μW

Carbon Nanotube Field-Effect Transistors (CNFETs) are highly promising to improve the energy efficiency of digital logic circuits. Here, we quantify the Very-Large-Scale Integrated (VLSI) circuit-level energy efficiency of CNFETs versus advanced technology options (ATOs) currently under consideration [e.g., silicon-germanium (SiGe) channels and progressing from today's FinFETs to gate-all-around nanowires/nanosheets]. We use industry-practice physical designs of digital VLSI processor cores in future technology nodes with millions of transistors (including effects from parasitics and interconnect wires) and technology parameters extracted from experimental data. Our analysis shows that CNFETs are projected to offer 9× energy-delay product (EDP) benefit (~3× faster while simultaneously consuming ~3× less energy) compared to Si/SiGe FinFET. The ATOs provide <;50% EDP benefits. All analyses are performed at the same off-state leakage current density (≤100 nA per micron of FET width) and power density (≤100 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area). This analysis provides insights into the sources of CNFET EDP benefits and addresses key questions for deeply-scaled technologies. For instance, while contact resistance is a concern for sub-10 nm nodes, CNFETs still provide up to 6.0× EDP benefit (versus Si/SiGe FinFETs) using CNFET contact resistance values already experimentally achieved for 9 nm contact length.

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and \(\overline {Q}\). The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10− 18 J and 29.6 × 10− 18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40∘C to 120 ∘C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively.

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.