Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

Carbon nanotubes (CNT) field-effect transistor (CNTFET) could be a possible alternative to CMOS technology for future VLSI applications. In this work, a comparative study has been carried out on the effects of technology nodes and logic styles on power dissipation, delay, leakages, etc. The technology nodes that are considered here are 90 nm and 32 nm MOSFET technology, and 32 nm CNTFET technology. The logic families considered here are the conventional complementary metal-oxide-semiconductor (CMOS), complementary pass transistor logic (CPL) and transmission gate (TG). The digital circuits considered are NAND, NOR, XOR and MUX gates. HSPICE simulations have been carried out and observed that at 32 nm CNTFET technology, the least power, worst-case delay and least PDP are found as 15.5 nW, 3.11 ps and 0.048 aJ, respectively. It is witnessed that CNTFET-based logics are superior compared to other logic families at different technology nodes.

The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematics using graphene nanoribbon field effect transistors (GNFETs). The dimer line of graphene nanoribbon (GN) is used to control the threshold voltage of GNFETs. Four quaternary logic inverter circuits such as standard quaternary inverter (SQI), intermediate quaternary inverter (IQI), positive quaternary inverter (PQI) and negative quaternary inverter (NQI) along with the NAND and NOR circuits are proposed. Furthermore, the quaternary half adder circuit is designed that helps to develop complex designs. The HSPICE simulator is utilized for simulating the proposed designs to obtain the performances such as delay, power and power delay product (PDP). The obtained circuit performances are compared with carbon nanotube FETs (CNFETs) based circuits. The comparison results show that the proposed GNFET circuits achieved 53.51% of overall performance improvement over the CNFET circuits.

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed with a combination of synthesized low-power ternary logic gates. The proposed methodology is applicable to both unbalanced (0, 1, 2) and balanced (−1, 0, 1) ternary logic. To verify the improvement in energy efficiency, we have designed various ternary arithmetic logic circuits using the proposed methodology. The proposed ternary full adder has a significant improvement in the power-delay product (PDP) over previous designs. Ternary benchmark circuits have been designed to show that complex ternary functions can be designed to more efficient circuits with the proposed methodology.

Due to extraordinary physical and electrical properties, carbon nanotubes have become one of the most promising technologies that might someday pick up where conventional CMOS devices leave off. This paper details analysis of power and delay performance of carbon nanotube field effect transistor- based universal logic gates (NAND and NOR gates). Though electrolyte-gated carbon nanotube field effect transistor have exhibited the highest performance than top-gated and back-gated carbon nanotube field effect transistor, the work demonstrates that energy delay product and switching time performance of 30nm channel length top-gated carbon nanotube field effect transistor - based NAND gate is much better than 20nm channel length electrolyte-gated carbon nanotube field effect transistor technology. As the performance of p type carbon nanotube field effect transistor is better than n type carbon nanotube field effect transistor, 30nm channel length top-gated carbon nanotube field effect transistor-based NOR gate is 4% faster than corresponding NAND gate and its energy delay product is 46% lesser than that of NAND gate.

The novel characteristics of CNTFET have eliminated many technological and fundamental hindrances being faced by CMOS transistors. CNTFET is emerging as prospective replacement for CMOS transistors in digital circuits and systems. This chapter introduces design of CNTFET-based basic logic gates. The basic logic gates analyzed are inverter, NAND, and NOR gates. The designed gates are evaluated in terms of delay, power consumption, and figure-of-merit power-delay-product (PDP). The standard H-SPICE CNTFET model of Stanford University has been used for all simulations. The impact of dielectric material variations on performance parameters of carbon nanotube field effect transistor based universal gates has been analyzed. Comparison between CMOS and CNTFET-based logic circuits is carried out for different dielectric material at 16 nm technology node.

Ternary Logic is the best and suitable alternative for binary logic. Binary Logic consists of 2 logic states 0 and 1 whereas ternary logic contains three states logic 0, 1 and 2. The advantages of Ternary over binary logic is it improves switching speed. This technique helps to reduce the computation steps, complexity and chip area. This paper is a study of CNTFET based ternary logic gate and improved impact on power and delay. A ternary NAND, NOR Gates are designed using Carbon nanotube transistors. The TNAND and TNOR gate circuits are simulated using the HSPICE tool. The performance parameters of the TLG using Carbon Nanotube FETs in terms of Delay are 621ps, 20.66ps, in terms of power are 0.47μW, 0.53μW

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.

This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.

Carbon Nanotube Field Effect Transistors (CNFETs) are considered to be an ideal choice for implementation of Multi-valued logic circuits, as by using CNFETs multiple thresholds can be obtained by altering the dimensions of the carbon nanotube. Implementation of various CNFET based Ternary Arithmetic circuits like Adders and Multipliers is extensively researched upon. The existing design for a CNFET based Multiplier is based on the classical Wallace approach which uses 3:1 Multiplexers along with Unary operators of Ternary logic. In this paper, design of a novel low power Single-Trit Multiplier and a Three-Trit Multiplier is proposed which uses a 2:1 Multiplexer based design approach. This design shows considerable improvement in terms of power consumption. From the Hspice simulation results, it is noted that the proposed Single-Trit Multiplier design results in up to 99% reduction in Power consumption, 56% reduction in Delay and 99.8% reduction in Power-Delay Product (PDP) when compared to an existing Single-Trit Multiplier. Proposed Three-Trit Multiplier results in savings in power consumption up to 98.2% and 98. 5% reduction in PDP when compared to Three-Trit Multiplier design in the existing literature.

Enhancing high-speed digital systems: MVL circuit design with CNTFET and RRAM

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

In this paper it is proposed the implementation in Matlab & Tools environment, by using Simulink and Simscape plug-ins, of empirical models of the Carbon Nanotube Field Effect Transistor (CNTFET) in order to evaluate the capability of this very interesting design and simulation environment to easily design the most advanced generation of digital electronic circuits. Empirical models of electronic devices are particularly suitable for the Computer Aided Design (CAD) of digital electronic circuits. They are generally very compact, fast and accurate, without any physical approximation, and then they can be easily implemented in circuit simulators. The paper aims at describing the core of a possible CAD tool for digital circuits using CNTFETs, designed by the author, and at evaluating its suitability and usefulness by design examples. Therefore, they have been implemented two models of CNTFETs in Matlab & Tools environment and it has been performed the design of basic digital logic gates and memory elements. One of the two models has been developed by the author and already validated. The other model has been developed by valuable authors at Standford University and is used for comparisons. Results show the great usefulness of the empirical approach and of the Matlab & Tools environment for the quick and easy design of digital electronic circuits using CNTFETs.

The modern era, Carbon Nano-tube Field effect transistor (CNT FET) play a significant role in circuit design for various aspects. As the demand for high-speed and energy-efficient arithmetic units develops, it becomes critical to investigate novel adder architectures. Ternary arithmetic, with its potential for increased computational density and shorter carry propagation delays, has emerged as a possible alternative to binary arithmetic. The overview of the ternary logic has discussed initial phase, the next important parameters like propagation delay, power dissipation, power delay product. Energy delay product analysis has elaborated. Further literature survey has done from fast decade on ternary logic circuits, which can work efficiently with low power consumption. Then it digs into the architectural complexities of TCLAs, focusing on the methods for ternary carry look-ahead and efficient ternary sum generation. Various optimization strategies for increasing the speed and area efficiency of TCLAs are also examined, such as hybrid carry generation schemes and transistor-level optimizations.

The quest for efficient technologies beyond the traditional CMOS (Complementary-Metal-Oxide-Semiconductor) technology has led researchers to explore newer technologies like the CNFET(Carbon-Nanotube-Field-Effect-Transistor). CNFETs are being used to design and implement various ternary logic circuits. Multivalued logic (MVL) requires multiple threshold voltages that are possible to obtain using CNFETs by modifying the physical dimensions of their CNTs (Carbon Nano Tubes). The ternary sequential logic circuits like ternary D-latch, D-flipflop, and counters existing in literature have been implemented either using STIs (Standard Ternary Inverters) or successor-predecessor circuits. This paper proposes a new design methodology for a ternary D-flipflop that uses a ternary buffer and two STIs designed using two power supplies. Two hybrid architectures for ternary D-flipflop designs have also been proposed that are implemented using a combination of ternary buffer, STIs and successor-predecessor circuits. Using these ternary D-flipflop designs, ternary 3- trit synchronous and asynchronous counters are designed in this paper. The proposed designs are simulated using HSPICE and a standard Stanford CNFET model. The proposed ternary D-flipflops show an improvement of up to 93.5% in power, up to 44.7% in delay and up to 94.3% in PDP compared to existing designs.

Ternary logic has become a promising alternative to traditional binary logic due to low power consumption and reduced circuits such as interconnects and chip areas. The efficiency of the multiplier circuit can be much better using a ternary logic system. Carbon nanotube field-effect transistor (CNTFET) is a promising technology as it achieves more advantages than MOSFET due to its low off-current features such as low power and high performance. This paper presents a comparative study of four implementations of a 1-trit multiplier based on CNTFET technology. The comparison is performed in terms of area, power, delay, and power delay product versus variation of supply voltage and temperature. The simulation results show that the proper PDP can be achieved using the transmission gate based multiplier. All the designs are implemented using the Virtual Source CNTFET (VS-CNTFET) Stanford model.