Code Optimization by Integer Linear Programming

With the rapid evolution of large language models (LLM), reinforcement learning (RL) has emerged as a pivotal technique for code generation and optimization in various domains. This paper presents a systematic survey of the application of RL in code optimization and generation, highlighting its role in enhancing compiler optimization, resource allocation, and the development of frameworks and tools. Subsequent sections first delve into the intricate processes of compiler optimization, where RL algorithms are leveraged to improve efficiency and resource utilization. The discussion then progresses to the function of RL in resource allocation, emphasizing register allocation and system optimization. We also explore the burgeoning role of frameworks and tools in code generation, examining how RL can be integrated to bolster their capabilities. This survey aims to serve as a comprehensive resource for researchers and practitioners interested in harnessing the power of RL to advance code generation and optimization techniques.

This paper presents a new heuristic, concurrent, iterative loop-based scheduling and allocation algorithm for high-level synthesis of digital signal processing (DSP) architectures using heterogeneous functional units. In a heterogeneous architecture, functional units could be either bit-serial or digit-serial or bit-parallel. We assume that a library of functional units based on heterogeneous implementation style is available. Experiments show that this new heuristic synthesis approach generates optimal and near-optimal area solutions. Although optimum synthesis of such architectures were proposed recently using an integer linear programming (ILP) model, our method can produce similar solutions in one to two orders of magnitude less time, at the expense of sacrificing the cost optimality. We compare the solutions generated by the proposed algorithm with the optimal solutions generated by the ILP approach and other recent techniques. We have incorporated this new algorithm into the Minnesota ARchitecture Synthesis (MARS-II) system.

Digital Signal Processors (DSPs) are a family of embedded processors with tight constraints on memory, area, and cost. Many such systems have irregular addressing modes where base-plus-offset mode is not supported. However, they have address generation units (AGUs) that can perform auto-increment/decrement address arithmetic instructions in parallel with the same Load/Store instruction. This can be utilized to reduce the number of explicit address arithmetic instructions to minimize the code size. An effective technique for optimized code generation is offset assignment. This technique reduces the code size by finding an offset assignment that can maximally utilize auto-increment/decrement. In this paper, we present an optimal integer linear programming (ILP) solution to the offset assignment problem with variable coalescing and variable permutation. Experimental results on several benchmarks show the effectiveness of our techniques.

The architecture of a new code generator for digital signal processors (DSPs) and the motivations for a new high-level specification environment are described. Graphical signal flow graph (SFG) and the Silage language are used as input specifications. Extremely efficient code can be generated for existing commercially available DSP processors. Because of the DSP knowledge embedded in the system, the code generated is about five to 50 times faster than the one produced with conventional C compilers and is comparable to the code generated by DSP experts. The code generator comprises part of a powerful DSP design environment that allows the user to choose a solution based on one or more commercially available DSP processors or to select one of the DSP silicon compilers available in this framework. System-level or bit true software simulators or hardware accelerators can also be called at different stages of the design. >

Nearly all personal computer and workstation processors, and virtually all high-performance embedded processor cores, now embody instruction level parallel (ILP) processing in the form of superscalar or very long instruction word (VLIW) architectures. ILP processors put much more of a burden on compilers; without heroic compiling techniques, most such processors fall far short of their performance goals. Those techniques are largely found in the high-level optimization phase and in the code generation phase; they are also collectively called instruction scheduling. This paper reviews the state of the art in code generation for ILP parallel processors. Modern ILP code generation methods move code across basic block boundaries. These methods grew out of techniques for generating horizontal microcode, so we introduce the problem by describing its history. Most modem approaches can be categorized by the shape of the scheduling region. Some of these regions are loops, and for those techniques known broadly as are used. Software Pipelining techniques are only considered here when there are issues relevant to the region-based techniques presented. The selection of a type of region to use in this process is one of the most controversial questions in code generation; the paper surveys the best known alternatives. The paper then considers two questions: First, given a type of region, how does one pick specific regions of that type in the intermediate code. In conjunction with region selection, we consider region enlargement techniques such as unrolling and branch target expansion. The second question, how does one construct a schedule once regions have been selected, occupies the next section of the paper. Finally, schedule construction using recent, innovative resource modeling based on finite-state automata is then reexamined. The paper includes an extensive bibliography.

The model-based approach has been widely applied to the design of software. However, most of these approaches depend on simulation and manual code implementation, which reduces the efficiency and quality of software. In this paper, we present a new model-based approach, which automatically generates the executable C++ code running on the popular Robot Operation System (ROS). Our approach consists of three phases: modeling, verification, and automatic code generation. In the modeling phase, the internal interaction behaviors of robot systems are modeled as a network of timed automata. In the verification phase, the safety requirements are formalized and verified. In the code generation phase, a code generation tool can generate executable C++ code from the verified timed automata model. It bridges the gap between the formal model and the error-prone system implementation. Compared with existing method, the code generator provides the abstractions and mapping of ROS instructions, which realize the seamless connection between the generated code and ROS. The tool also supports most of the complex structures and advanced features of timed automata such as timer, committed location, and synchronous action. For evaluation, a real-industrial robot application of grasping a cup is conducted using our model-based design method, and the generated code can be directly deployed and successfully accomplishes the grasping task.

A high-level built-in self-test (BIST) synthesis involves several tasks such as system register assignment, interconnection assignment, and BIST register assignment. Existing high-level BIST synthesis methods perform the tasks sequentially at the cost of global optimality. We proposed a new approach based on an integer linear programming (ILP). Our method achieves optimal solutions for most circuits in hardware overhead, but it takes a long processing time. In this paper, we present a heuristic method to address this problem. The heuristic partitions a given data flow graph into smaller regions based on control steps and applies the ILP for each region successively. Our heuristic reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised. We present experimental results for six circuits and compare the results with other BIST synthesis methods.

Coordinated lane-changing scheduling of multilane CAV platoons in heterogeneous scenarios

This paper describes a system that accepts compact specifications of an intermediate code and target machine and produces program code for an integrated code generator and peephole optimizer. A compiler for most of C uses this packa.ge. It emits code comparable to PCCI’S, but it runs over five times faster on preliminary benchmarks. This compiler also runs over twice as fast as a version of pcc2 with a hand-coded, VAX-specific code generator. The code generators are produced as follows. A programmer describes a naive code generator by means of a non-procedural specification. The programmer also prepares a machine description for a retargetable peephole optimizer [2]. These two systems are used together to compile a testbed, and the compiler records each peephole optimization as it is made. This record and the specification of the naive code generator are compiled into a fast, integrated code generator and optimizer. This production code generator then takes the place of the slower “training” version. The production code generator and optimizer are integrated to the point that the code to be generated is communicated from one to the other by encoding it in the program counter, which obviates most inter-phase communication costs. Interpretive peephole optimizers have been driven by traces from retargetable peephole optimizers [3] and integrated with interpretive code generators [4], but the current work is distinguished by the production of a hard-coded, optimizing code generator. Historically, retargetable code generators (i.e., those not largely rewritten for each new machine)

This paper proposes the optimal design of lightpath Routing and Wavelength Assignment (RWA) problem in Wavelength Division Multiplexing (WDM) networks without wavelength conversion. We formulate RWA as a mixed Integer Linear Programming (ILP) problem where the objective is to minimize the cost of wavelength assignment to the fiber links in the network. The Lagrangean relaxation technique and the optimization-based heuristics are used to solve this problem. Two sets of computational experiments are performed to test the algorithms for the maximum carried traffic and minimum wavelength requirements in three different network topologies (GTE, ARPA, OCT network). Based on solution quality to the computational experiments, the error gaps between the upper bound and the lower bound are close enough that the near optimal solutions could be obtained. On the other hand, we also show that the solution quality degrade gracefully under more and more heavy traffic network environment. By assessing solution quality and the computational time, we propose the efficient and effective optimization-based algorithms based on the Lagrangean relaxation method for the RWA problem in the WDM networks without wavelength conversion.

Disclosed is a stringed instrument (100) with embedded digital signal processing (DSP) modeling capabilities. The stringed instrument (100) has a body (102) and a plurality of strings (106) and each of the plurality of strings (106) is respectively coupled to a pickup of a polyphonic pickup (110). The polyphonic pickup (110) is used to detect a vibration signal for each string (106). An A/D converter converts the detected vibration signal of a string into a digital string vibration signal. Further, a digital signal processor (120) is located within the body of the stringed instrument to process the digital string vibration signal. Particularly, the digital signal processor (120) is used to process the digital string vibration signal such that the corresponding string tone of one of a plurality of selectable stringed instruments may be emulated. The emulated digital tone signal is then converted to analog form to create an emulated analog tone signal for output to an amplification device.

Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules, mostly due to the limitation of the processor's internal structures, must be observed to achieve the full performance. These include the proper selection of operand data types, efficient usage of data and address registers, and novel instruction scheduling to support parallel execution without pipeline conflicts. In this paper, a progressive code generation scheme based on a simulated evolution algorithm is devised. In this scheme, the selection of operand data type is embedded in instruction scheduling so that appropriate choices can be made to support parallel instruction. Instruction scheduling and register allocation, however, are performed in an interleaving and iterative manner. In each iteration, the generated code quality is evaluated and the inferior part is rescheduled. Tested benchmark programs indicate that our scheme can outperform the TI DSP processor C compiler and generate very efficient assembly codes.

In electronic design automation, the problem of double patterning lithography (DPL) can be formulated as follows. Two features of a layout should be assigned different colors if their spacing is less than the minimum coloring spacing. Because only two colors are used in DPL, a layout may contain a pattern which cannot be assigned a color. To resolve the conflict, a stitch is used to split a feature into two parts and then the two parts can be assigned different colors. However, stitches will cause yield loss. Moreover, a balanced coloring will lead to better patterning quality. In brief, the focus of DPL is the reduction of conflicts and stitches and the balance of colors. In this paper, we propose an integer linear programming (ILP)-based algorithm to address the DPL problem with graph theory. Because it is time-consuming to generate a solution for a whole layout with ILP, we extract faces from the conflict graph which is used to represent a layout. Thus, an ILP formulation for face is proposed. Finally, these faces are merged according to the negotiation on the quality of solution. Experimental results show that, compared to the method without considering the balance of color, our algorithm can generate solutions with 15% less area difference averagely with the same quality of conflicts and stitches. Moreover, compared to the previous algorithm of layout decomposition, our algorithm can reduce the number of conflicts by 29%, the number of stitches by 12% averagely

Integer Linear Programming (ILP) is commonly used in high level and system level synthesis. It is an NP-Complete problem (in general cases). There exists some tools that give an optimal solution for small ILP formulations. Nevertheless, these tools may not give solutions for complex formulations. In this paper, we present a solution to overcome the problem of complexity in ILP formulations. We propose a partitioning methodology based on a constraint graph representing all the constraints included in any ILP formulation. To direct the partitioning, the constraint graph nodes are grouped to represent Data Flow Graph (DFG) nodes. This reduced constraint graph can be used to partition any ILP formulation based on DFG. We illustrate this method on ILP formulation for scheduling. Results on ILP scheduling formulations are promising.

Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors consist of multiple phases for cluster assignment, register allocation and instruction scheduling. Most of these approaches need additional re-scheduling phases because they often do not impose finite resource constraints in all phases of code generation. These phase-ordered solutions have several drawbacks, resulting in the generation of poor performance code. Moreover the iterative/back-tracking algorithms used in some of these schemes have large turning times. In this paper we present CARS, a code generation framework for Clustered ILP processors, which combines the cluster assignment, register allocation, and instruction scheduling phases into a single code generation phase, thereby eliminating the problems associated with phase-ordered solutions. The CARS algorithm explicitly takes into account all the resource constraints at each cluster scheduling step to reduce spilling and to avoid iterative re-scheduling steps. We also present a new on-the-fly register allocation scheme developed for CARS. We describe an implementation of the proposed code generation framework and the results of a performance evaluation study using the SPEC95/2000 and MediaBench benchmarks.