Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units

Summary form only given. In high level synthesis for real-time digital signal processing (DSP) architectures using heterogeneous functional units (FUs), an important problem is how to assign a proper fit type to each operation of a DSP application and generate a schedule in such a way that all requirements can be met and the total cost can be minimized. We propose a two-phase approach to solve this problem. In the first phase, we solve heterogeneous assignment problem, i.e., how to assign a proper FU type to a DSP application such that the total cost can be minimized while the timing constraint is satisfied. In the second phase, based on the assignments obtained from the first phase, we propose a minimum resource scheduling algorithm to generate a schedule and a feasible configuration that uses as little resource as possible. We prove heterogeneous assignment problem is NP-complete and propose several algorithms to solve it. The experiments show that algorithm DFG-assign-repeat is the best that gives a reduction of 25.7% on total cost compared with the previous work.

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

The weighted independent domination problem: Integer linear programming models and metaheuristic approaches

A CMOS gate array architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate arrays.

A lot of modern ultrasonic measurement (UM) applications use digital signal processing (DSP). In many cases DSP comprises a significant part of system hardware and cost, also it sets certain restrictions on measurement speed and signal-to-noise ratio. This paper deals with the influence of the DSP into signal-to-noise ratio and its relevant characteristicsIt presents a concept of DSP exploration in applications. According to this concept the integrated model UM application - DSP architecture is used to select the rational DSP following the application requirements. The exploration is illustrated with the correlational time delay estimation task. The exploration method was suggested and applied in two scientific projects that have done by Ultrasound Research Center and DSP Laboratory at Kaunas University of Technology. During these projects the ultrasonic vision system for mobile robot (project INCO-COPERNICUS No. ERB IC15-CT96-0726) and high precision ultrasonic gas flowmeter have been designed. In both cases signal processing was necessary and the DSP design presented quite serious problem. The model is implemented in software and provides high flexibility. It can be modified for different DSP methods and signals, therefore, it is applicable for the design of various systems.

In this work, we propose an integer linear programming (ILP) model to schedule a set of weakly-hard real-time tasks on a heterogeneous multiprocessor system to minimize energy consumption with the predictable performance. The ILP model provides an optimal solution in terms of energy consumption by selecting the appropriate frequency for each task with (m,k) weakly-hard deadline constraint.

This chapter presents a linear-programming-based optimal solution for an Optimal Placement Problem (OPP) of Synchrophasors or Phasor Measurement Units (PMU). With the increasing use of Synchrophasors for smart-grid monitoring and control, the problem with PMU placement has become a major concern due to its large installation costs. This chapter utilizes an Integer Linear Programming (ILP) approach to find optimal solutions. We show that the performance of our LP constraints and the formulation makes the ILP approach very attractive for smaller utilities that have limited budgets. This is shown using with and without zero-injection cases in programmed AMPL language using CPLEX solver. We also propose an Optimal Redundancy Criterion (ORC) which assists utilities with providing redundant observability for critical buses in the system. Our approach yields full and redundant observabilities within a few milliseconds for different cases, such as IEEE 300 test systems and an Indian power grid.

Current mobile phone applications demand high performance from the DSP, and future generations are likely to require even greater throughput. However, it is important to balance these processing demands against the requirement of low power consumption for extended battery lifetime. A novel low‐power digital signal processor (DSP) architecture CADRE (Configurable Asynchronous DSP for Reduced Energy) addresses these requirements through a multi‐level power reduction strategy. A parallel architecture and configurable compressed instruction set meets the throughput requirements without excessive program memory bandwidth, while a large register file reduces the cost of data accesses. Sign‐magnitude representation is used for data, to reduce switching activity within the datapath. Asynchronous design gives fine‐grained activity control without the complexities of clock gating, and gives low electromagnetic interference. Finally, the operational model of the target application allows for a reduced interrupt structure, simplifying processor design by avoiding the need for exact exceptions.

Power dissipation is becoming a limiting factor in the realisation of VLSI systems. The principal reasons for this are maximum operating temperature and, for portable applications, battery life. Because of the relatively greater complexity, the power dissipation in Digital Signal Processing (DSP) applications is of special significance, and low-power design techniques are now emerging. This paper provides an overview of these techniques and aims to serve as a bibliography of the key papers relevant to low-power DSP design. In addition, the paper presents indications for potential design directions bearing in mind the architectural complexity and the speed requirements of today's systems. CMOS logic is assumed since this is currently the most commonly used VLSI technology due to its high degree of integration which is in turn allowed by its scaling properties and low power dissipation.

The code quality of many high-level language compilers in the field of digital signal processing is not satisfactory. This is mostly due to the complexity of the code generation problem together with the irregularity of typical DSP architectures. Since digital signal processors mostly are traded on the high volume consumer market, they are subject to serious cost constraints. On the other hand, many embedded applications demand high performance capacities. Thus, it is very important that the features of the processor are exploited as efficiently as possible. By using integer linear programming (ILP), the deficiencies of the decoupling of different code generation phases can be removed, since it is possible to integrate instruction scheduling and register assignment in one homogeneous problem description. This way, optimal solutions can be found-albeit at the cost of high compilation times. Our experiments show, that approximations based on integer linear programming can provide a better solution quality than classical code generation algorithms in acceptable runtime for medium sized code sequences. The experiments were performed for a modern DSP, the Analog Devices ADSP-2106x.

We present new integer linear programming (ILP) models for NP-hard optimisation problems in instances of the Stable Marriage problem with Ties and Incomplete lists (SMTI) and its many-to-one generalisation, the Hospitals/Residents problem with Ties (HRT). These models can be used to efficiently solve these optimisation problems when applied to (i) instances derived from real-world applications, and (ii) larger instances that are randomly-generated. In the case of SMTI, we consider instances arising from the pairing of children with adoptive families, where preferences are obtained from a quality measure of each possible pairing of child to family. In this case, we seek a maximum weight stable matching. We present new algorithms for preprocessing instances of SMTI with ties on both sides, as well as new ILP models. Algorithms based on existing state-of-the-art models only solve 6 of our 22 real-world instances within an hour per instance, and our new models incorporating dummy variables and constraint merging, together with preprocessing and a warm start, solve all 22 instances within a mean runtime of a minute. For HRT, we consider instances derived from the problem of assigning junior doctors to foundation posts in Scottish hospitals. Here, we seek a maximum size stable matching. We show how to extend our models for SMTI to HRT and reduce the average running time for real-world HRT instances by two orders of magnitude. We also show that our models outperform by a wide margin all known state-of-the-art models on larger randomly-generated instances of SMTI and HRT.

With the enhancement in channel bandwidth and mobile devices, more broadcast applications will be deployed in the wireless mesh networks (WMNs). While traditional approaches focus on finding a single broadcast tree in the network, we aim at maximizing the number of broadcast trees/calls that can be carried. In this paper, we first formulate an Integer Linear Program (ILP) for solving the minimum-channel-utilization broadcast tree problem in multi-channel multi-interface WMNs. In our ILP, channel assignment, routing, and scheduling are jointly considered for finding a broadcast tree that can minimize the maximum channel utilization. Intuitively, this balances all the accepted traffic load in the network, which in turn maximizes the chance of accepting future calls. However, solving ILP usually takes time and is less suitable for a system with real-time call arrival. An efficient heuristic algorithm is then designed. Our simulation results show that the proposed heuristic gives real-time response and provides comparable good performance as the ILP approach.

Given a set $\mathcal{T}= \{T_{1}, T_{2}, . . .\, T_{m}\}$ of phylogenetic trees with the same leaf-label set X, we wish to remove some leaves from the trees so that there is a tree T with leaf-label set X displaying all the resulting trees. Note that different leaves may be removed from different input trees. One objective is to minimize the total number of leaves removed from the trees, while the other is to minimize the maximum number of leaves removed from an input tree. Chauve et at. [2] refer to the problem with the first (respectively, second) objective as AST-LR (respectively, AST-LR-d), and show that both problems are NP-hard. They further present algorithms for the parameterized versions of both problems. In this paper, we point out that their algorithm for the parameterized version of AST-LR is flawed. We then design integer-linear programming (ILP) models for AST-LR and AST-LR-d, and discuss speedup issues when using popular ILP solvers (say, GUROBI or CPLEX) to solve the models. Our experimental results show that our ILP approach is relatively efficient.

We describe a design problem arising in the color printing industry and discuss a number of integer linear programming and constraint programming approaches to its solution. Despite the apparent simplicity of the problem it presents a challenge for both approaches. We present results for three typical cases and show that the constraint programming approach provides better results, although in some cases after considerable handcrafting. We also show that the results obtained by constraint programming can be improved by a simple goal programming model.

In high-level synthesis for real-time embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied execution time as a probabilistic random variable and solves the heterogeneous assignment with probability (HAP) problem. The solution of the HAP problem assigns a proper FU type to each task such that the total cost is minimized while the timing constraint is satisfied with a guaranteed confidence probability. The solutions to the HAP problem are useful for both hard real-time and soft real-time systems. Optimal algorithms are proposed to find the optimal solutions for the HAP problem when the input is a tree or a simple path. Two other algorithms, one is optimal and the other is near-optimal heuristic, are proposed to solve the general problem. The experiments show that our algorithms can effectively reduce the total cost while satisfying timing constraints with guaranteed confidence probabilities. For example, our algorithms achieve an average reduction of 33.0% on total cost with 0.90 confidence probability satisfying timing constraints compared with the previous work using the worst-case scenario.