Cognitive collaboration: A design methodology for future-oriented intelligent industrial systems

: Minnesat is the micro-satellite that was designed by the University of Minnesota as part of UNP-4. The mission of Minnesat was to validate the use carrier phase GPS technology to mechanize a compact and accurate attitude determination system. In a broader sense, the objective of this work was to also demonstrate a design methodology for miniature spacecraft navigation, guidance and control systems which integrate the vehicle design process with that of the process of designing the avionics. Minnesat was presented to the US Air Force at the UNP-4 flight competition review. Although Minnesat was not the winning design, it accomplished its scientific and educational goals. The research work of designing compact GPS attitude determination systems continues at the University of Minnesota building on the success of Minnesat. On the other hand, students that were participants in the UNP-4 competition are now employed by various aerospace corporations, are enrolled in aerospace engineering graduate programs or are completing advanced degrees in engineering and science programs.

This paper reviews the state of the art of field- programmable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic.

In this paper, we propose a new generalized design methodology of intelligent robust fuzzy control systems based on quantum genetic algorithm (QGA) called quantum fuzzy model that enhance robustness of fuzzy logic controllers. The QGA is adopted because of their capabilities of directed random search for global optimization to find the parameters of the shape and width of membership functions and rule set of the FLC to obtain the optimal fuzzy controller simultaneously. We test the optimal FLC obtained by the quantum computing applied on the control of dynamic balance and motion of cart-pole balancing system. We compare the proposed technique with existing mamdani fuzzy logic controller which is designed through conventional genetic algorithm. Simulation results reveal that QGA performs better than conventional GA in terms of running speed and optimizing capability.

For biometric person authentication, system design and assessment methodology form essential part of the entire process. We design a performance evaluation methodology for face recognition system based on identification and verification model. To validate our model, we designed a projection-based face recognition system which requires numerous design decisions. We explicitly state the design decisions by introducing a generic modular face recognition system. We explore various implementations for preprocessing, representation and recognition modules. Our experiment includes major factors for system design and assessment: (1) changing the illumination normalization preprocessing; (2) varying the number of features in the representation; and (3) changing the similarity measure in recognition process. We perform experiments and present results for identification and verification scenarios.

Sustainable production networks: A design methodology based on the cooperation among stakeholders

In this paper a design method for mechatronic functions in an early design phase under consideration of the requirements of functional safety is proposed [14]. The goal of the method is to discover threats for the safety goals and to prove or optimize the diagnostic mechanisms. At the current design process a lifetime endurance test is performed in a late project phase. In order to avoid unexpected late design changes the method should be applied in an early design phase. The method is an additional way to avoid design failures for E/E functions with special focus on aging in the field of functional safety applications. The method is developed out of three standards VDI 2221 methodology for development and construction of technical systems and products [1]), VDI 2206 design methodology for mechatronic systems [2] and the ISO 26262 road vehicles - Functional Safety [3] by using the V-Model. Furthermore, a core element of the design method is simulating aging effects by applying VHDL – AMS. To demonstrate the design methodology a sensor out of the EGAS function is chosen as a safety relevant automotive system. The limitation is the availability of aging data for electrical components.i

A hierarchical design methodology for multiple microprocessor system

The design of an elevator system heavily relies on the calculation of the round-trip time under up-peak (incoming) traffic conditions. The round-trip time can either be calculated analytically or by the use of Monte Carlo simulation. However, the calculation of the round-trip time is only part of the design methodology. This paper does not discuss the round-trip time calculation methodology as this has been addressed in detail elsewhere. This paper presents a step-by-step automated design methodology which gives the optimum number of elevators in very specific, constrained arrival situations. A range of situations can be considered and a judgement can be made as to what is the best cost–performance tradeoff. It uses the round trip value calculated by the use of other tools to automatically arrive at an optimal elevator design for a building. It employs rules and graphical methods. The methodology starts from the user requirements in the form of three parameters: the target interval; the expected passenger arrival rate (AR%) which is the passenger arrival in the busiest 5 min expressed as a percentage of the building population; and the total building population. Using these requirements, the expected number of passengers boarding an elevator car is calculated. Then, the round-trip time is calculated (using other tools) and the optimum number of elevators is calculated. Further iterations are carried out to refine the actual number of passengers boarding the elevator and the actual achieved target. The optimal car capacity is then calculated based on the final expected passengers boarding the car. The HARint plane is presented as a graphical tool that allows the designer to visualise the solution. Three different rated speeds are suggested and used in order to explore the possibility of reducing the number of elevator cars. Moreover, the average passenger travel time is used to indicate the need for zoning of buildings. Practical application: This paper has an important application in allowing the designer to arrive at the optimum design for the elevator system using a clearly defined methodology. This ensures that the number of elevators, their speed and their capacity are optimised, thus ensuring that the cost of the elevator system and the space it occupies within the building are minimised. The method also employs a graphical method (the HARint) in order to allow the designer to visualise the optimality and the feasibility of the different design options.

This paper presents a new methodology for design and implementation of signal processing systems on system-on-chip (SoC) platforms. The methodology is centered on the use of lightweight application programming interfaces for applying principles of dataflow design at different layers of abstraction. The development processes integrated in our approach are software implementation, hardware implementation, hardware-software co-design, and optimized application mapping. The proposed methodology facilitates development and integration of signal processing hardware and software modules that involve heterogeneous programming languages and platforms. As a demonstration of the proposed design framework, we present a dataflow-based deep neural network (DNN) implementation for vehicle classification that is streamlined for real-time operation on embedded SoC devices. Using the proposed methodology, we apply and integrate a variety of dataflow graph optimizations that are important for efficient mapping of the DNN system into a resource constrained implementation that involves cooperating multicore CPUs and field-programmable gate array subsystems. Through experiments, we demonstrate the flexibility and effectiveness with which different design transformations can be applied and integrated across multiple scales of the targeted computing system.

With continuing progress in VLSI and ASIC technologies, digital signal processing (DSP) algorithms have continued to find great use in increasingly wide application areas. DSP has gained popularity also in embedded systems although these systems set challenging constraints for implementations. Embedded systems contain limited resources, thus embedded DSP systems must balance tradeoffs between the requirements on computational power and computational resources. Energy efficiency has been important in batterypowered devices, but nowadays also the limited heat dissipation in small devices calls for low-power consumption. Successful implementation of DSP applications in embedded systems requires tailoring, which in turn sets challenges for design methodologies. For this special issue, we received 14 submissions and a collection of seven papers was finally accepted. The special issue is opened by “Observations on power-efficiency trends in mobile communication devices,” where the authors O. Silven and K. Jyrkka analyze the power consumption in the current mobile communication devices. Several bottlenecks in the current implementation style have been identified, thus the paper provides a good motivation for the following papers. In “The Sandbridge SB3011 platform,” the authors John Glossner et al. describe a system-on-a-chip (SoC) multiprocessor targeted as a software-defined radio platform. The platform provides solutions to the challenges in future mobile devices given in the previous paper. “A shared memory module for asynchronous arrays of processors” authored byMichael J. Meeuwsen et al. considers also chip multiprocessors. The presented shared memory module can be used for interprocess communication or to increase application performance by parallelizing computation. In “Implementing a WLAN video terminal using UML and fully automated design flow” by Petri Kukkala et al., an automated design flow for multiprocessor SoC is presented. The flow is based on UML descriptions and the authors demonstrate their design flow with a design case. Programming of chip multiprocessor platforms is considered in “pn: a tool for improved derivation of process networks” by Sven Verdoolaege et al. The paper discusses conversion of sequential programs to process networks allowing optimization of communication channels and buffers. In “A SystemC-based design methodology for digital signal processing systems,” the authors Christian Haubelt et al. describe a design flow for SoC designs containing automatic design space exploration, performance evaluation, and automatic platform-based system generation. The design flow is based on SystemC descriptions and the presented tools can automatically detect the underlying model of computation. Application-specific implementations are often used to speedup certain DSP tasks in embedded systems. In “Priority-based heading one detector in H.264/AVC decoding,” the authors Ke Xu et al. consider such implementations to speed up video decoding applications. The authors present a low-power decoder implementation for context-adaptive variable length coding defined in H.264 standard.

The authors propose the use of process models for DSS design. The kind of process models suggested are task structures and decision structures with simple graphical syntax and semantics. The process models form the basis for a coherent DSS design methodology, based upon the bounded rationality paradigm. The history of DSS and DSS design is discussed to form a theoretical position. The resulting methodology has been tested and evaluated in a laboratory experiment. The results of this evaluation will be used for continuous improvement of the methodology. >

A circuit-level methodology for hierarchical design and nodal simulation of microelectromechanical systems (MEMS) is presented. A layout-based schematic view is introduced as a geometrically intuitive MEMS representation that is transformed into a schematic suitable for behavioral simulation. As examples of the design methodology, suspended-MEMS inertial sensors, resonant actuators, and filters are designed using a small set of geometrically parameterized plate, beam, gap, and anchor elements. Effects of manufacturing variations are evaluated by simply changing parameter values of the elements.

The design methodology, analysis, and characterization of a radio frequency microelectromechanical systems (RF MEMS)-based reconfigurable antenna operating in the United States Public Safety bands are presented. It has two modes of operation with central frequencies of 718 and 4960 MHz, providing a high reconfigurable frequency ratio of ~7. This antenna is electrically small with lateral dimensions being ~λ/10 × λ/10 at 718 MHz. The reconfigurability between the modes is achieved by a single RF MEMS switch, which enables changing the length of the current flow path, thereby the resonance frequency is changed. The measurement results for impedance and radiation characteristics of the fabricated antenna prototype agree well with the simulations. The measured bandwidths of the antenna are 2.6% and 7.6% at 718 and 4960 MHz, respectively.

This paper takes as its starting point the paper published in the Phil. Trans. R. Soc . in 1972 entitled ‘A design methodology for ships and other complex systems’. It was written before computers had made much impact on the design as opposed to the analysis of ships and similarly large complex constructions. Not only have computers become synonymous with design practice, but there has also been a burgeoning of literature on all aspects of design, with it often being treated as a discipline in its own right. Taking ships in general, and the specific example of naval ship design in particular, a comprehensive design methodology is proposed. While giving due regard to the importance of management oriented design procedures, the methodology also draws on both engineering and architecture based versions of the design process. Particular attention is given to initial design since it is the most crucial phase in determining the overall configuration and because of its added importance with the current emphasis on concurrent engineering. The methodology proposed is considered to be flexible not only in the scope of its potential for application across a wide range of innovative solutions but also because of its basis in an architecturally derived synthesis. This methodology is contrasted with an alternative systems engineering based design approach, applicable to complex software oriented design but crucially lacking the capability to readily cater for the human element within the entity, which is always a significant concern in the design of physically large as well as complex systems.

High-speed digital devices require multiple voltage and frequency domains to accommodate the core logic and the input/output (I/O) circuitry for multiple interfaces. In addition, some of these interfaces are programmable to various speeds and signaling modes and they require multiple power supply voltages. These requirements create complex power delivery and signal distribution solutions. This paper proposes a design methodology for fast transient point of load (POL) power distribution architectures for microprocessors and fast switching logic. This paper presents an efficient power distribution system (PDS) design methodology that models the load, its point of load power converter, and the transporting system so that the entire system can be efficiently implemented in circuit simulation as a complete integrated setup for design optimization. Models for the voltage regulator module (VRM) and its transient response and stability, the active load with multiple power supply domains, and the power planes are discussed in detail. System voltage noise margin budgeting is also emphasized.