Comparative Analysis of Error Tolerance and Hardware Efficiency in Stochastic Computing-based Digital Filters

Stereo matching, utilized in diverse fields, poses a challenge to systems in resource-constrained environments due to the significant growth of computational load with image resolution. The challenge is crucial for the systems because fields utilizing stereo matching require short operational time for real-time applications and low power architecture. Stochastic computing (SC) is able to be a valuable approach to address the challenge by reducing the computational load by representing binary numbers with stochastic sequences, which are encoded as a probability value, and by leveraging the concept of mathematical probability. Also, it is possible for a system to be error-tolerant by utilizing the characteristics of stochastic computing. Therefore, in this paper, we propose an approach for lightweight and error-tolerant stereo matching with a hardware-implemented stochastic computing processor. To verify the feasibility and error tolerance of the proposed system, we implemented the proposed system and conducted experiments comparing depth maps with or without stochastic computing by calculating similarities. According to the experimental results, the proposed system indicated no significant differences in output depth maps and achieved an improvement in the depth maps from error-injected input images by an average of 58.95%. Therefore, we demonstrated that stereo matching with stochastic computing is feasible and error-tolerant.

An artificial intelligence approach for the design of infinite-impulse response (IIR) digital filters through Particle Swarm Optimization (PSO) is presented. IIR filter is essentially a digital filter with Recursive responses. Since the error surface of digital IIR filters is generally nonlinear and multimodal, so global optimization techniques are required in order to avoid local minima. This Paper is based on a heuristic way for the designing IIR filters. PSO is a powerful global optimization algorithm introduced in combinatorial optimization problems. This paper finds the optimum coefficients of IIR digital filter through PSO. It is found that the calculated values are more optimal than fda tool and GA available for the design of filter in MATLAB. Design of Low-pass and High-pass IIR digital filter is proposed to provide estimate of transition band. The simulation results of the employed examples shows an improvement on transition band. The stability of designed filters is described by the position of Pole-Zeros.

The article presents a technique for the synthesis of controlled digital recursive Chebyshev lowpassfilters of the first kind with an infinite impulse response. The frequency response of such filters hasripples in the passband and is as flat as possible in the stopband. Controllability is understood as anexplicit dependence of the filter coefficients on the cutoff frequency. The technique is based on the bilineartransformation of the transfer function of the analog low-pass filter prototype and the frequencytransformation of the amplitude-frequency characteristics of the obtained digital filter. The main idea ofthe technique is that for an analog prototype filter with a cutoff frequency of 1 rad/s, the parameters ofthe transfer function of biquadratic or bilinear links, which have the dimension of frequency, will benumerically equal to the correction factors for similar parameters of a controlled filter with an arbitrarycutoff frequency. As an example, the synthesis of a digital Chebyshev filter of the first kind of the fifthorder is considered. In this article, the transfer function of an arbitrary order filter is represented as acascade connection of II order links if the filter is of an even order. In the case of an odd order greaterthan one, one cascaded link of the first order is added. Despite the relative simplicity of the frequencyconversion, in its practical use for digital filters synthesized using computer-aided design of digital filters(or using reference books containing calculated prototype low-pass filters for various approximationsof the frequency response of an ideal low-pass filter), a series arises non-trivial specific momentsthat complicate the engineering use of this method of synthesizing controlled digital filters. Therefore, inaddition to the technique, a step-by-step algorithm has been developed that allows one to synthesize afilter without knowing these moments. The algorithm is implemented in the Mathcad environment; asan example, a digital recursive Chebyshev filter of the 1st kind of the 5th order is calculated.The example shows the calculated coefficients of a digital controlled low-pass filter, which explicitlydepend on the cutoff frequency, the amplitude-frequency characteristics of this filter and its lowfrequencyprototype converted into a filter with the same cutoff frequency, the amplitude-frequencycharacteristics are given in the same coordinates. Due to the good formalization of the algorithm, thelatter is suitable for the implementation of computer-aided design systems for controlled digitalChebyshev low-pass filters of the first kind.

We consider the design of stochastic computing (SC) hardware based on spintronic devices. SC offers low-cost implementations of arithmetic operations and high degrees of error tolerance. When compared to charge-based devices, spin-based devices could be lower energy, nonvolatile, etc. However, spin-based devices can be fundamentally more error prone than charge-based devices. The marriage of SC architectures and spin-based devices has the potential to produce information processing systems that are robust, low energy, and nonvolatile. In this paper, we investigate SC hardware comprised of nanomagnetic logic (NML) devices. NML is a “beyond-CMOS” technology that uses bistable magnets to store, process, and move binary information. We introduce new NML circuit structures that exploit unique features of the technology to efficiently realize hardware components required for an SC system (e.g., random number generation). We also benchmark NML-based SC circuits against other implementations, and illustrate how features that are unique to NML (e.g., inherent pipelining) can lead to improved performance. Our results indicate NML SC implementations achieve smaller area footprints with reduced energy and delay when compared to CMOS equivalents.

Deploying modern neural networks on resource-constrained edge devices necessitates a series of optimizations to ready them for production. These optimizations typically involve pruning, quantization, and fixed-point conversion to compress the model size and enhance energy efficiency. While these optimizations are generally adequate for most edge devices, there exists potential for further improving the energy efficiency by leveraging special-purpose hardware and unconventional computing paradigms. In this study, we explore stochastic computing neural networks and their impact on quantization and overall performance concerning weight distributions. When arithmetic operations such as addition and multiplication are executed by stochastic computing hardware, the arithmetic error may significantly increase, leading to a diminished overall accuracy. To bridge the accuracy gap between a fixed-point model and its stochastic computing implementation, we propose a novel approximate arithmetic-aware training method. We validate the efficacy of our approach by implementing the LeNet-5 convolutional neural network on an FPGA. Our experimental results reveal a negligible accuracy degradation of merely 0.01% compared with the floating-point counterpart, while achieving a substantial 27× speedup and 33× enhancement in energy efficiency compared with other FPGA implementations. Additionally, the proposed method enhances the likelihood of selecting optimal LFSR seeds for stochastic computing systems.

The well-known advantages of pipelining as applied to Finite Impulse Response (FIR) Residue Number System (RNS) arithmetic digital filters is extended to the important area of Infinite Impulse Response (IIR) digital filters through a new technique based on augmentation of the IIR transfer function. Through this technique, pipelined IIR filters based on RNS Read-Only-Memory (ROM) table look-up techniques can be designed which offer throughput rates equal to the table look-up time of the ROM's. This high-speed realization can be achieved even though the recursive filter algorithm requires multiple delays in realizing the output of the filter. For the example of a typical second-order IIR filter, the pipelined structure represents a five-fold increase in speed over standard techniques. Higher order realizations will yield proportionately higher speed improvements. Although the new technique does increase somewhat the hardware complexity of the filter, the increase in speed will often justify the additional hardware. The paper discusses the basic technique, stability considerations, and hardware realizations.

Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency, and soft output with a high hardware cost. Stochastic computing, as a form of approximate computing, provides a potential low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. By utilizing the frozen bits of polar codes and stochastic computing, multiple novel optimization methods are presented to further speed up convergence and increase the hardware efficiency.

A digital filter with infinite impulse response (IIR) was designed using the hybrid optimization methodology. The algorithm used is a dynamic-static topology of particle swarm optimization (DS-PSO) algorithm. The subject of non-linear mean square error (SE) optimization between the original and required filter responses in the passband, stopband, and transition band while tolerating permitted ripples in those bands was studied. Experimental results indicate a significant decrease in SE rates of passband and stopband with used technique, where SE values of digital IIR filter with DS-PSO were better than they were with evolutionary algorithms like DI-PSO (dynamic inertia PSO) and MDI-PSO (modified dynamic inertia PSO), at rates from about 50%–90% and 10%–90%, respectively, depending on filter's order. As a result, as compared to evolutionary algorithms, the suggested method creates greater fidelity coefficients and stable digital filters.

Digital infinite impulse response (IIR) filter have become the target of growing interest, because they often provide a much better performance and less computational cost than finite impulse response (FIR) filters. Since the problem of error surface of designing Digital IIR filters is generally nonlinear and multimodal, global optimization techniques are required in order to avoid local minima. In this paper, an evolutionary method based on Imperialist Competitive Algorithm (ICA) has been proposed to design Digital IIR filters. By adding a step to the standard ICA algorithm, its performance has been improved in searching solution space and convergence to the global minima. Simulation results show the efficiency of the proposed method to design Digital IIR filter.

Digital filters in communication link should be carefully designed, because small timing errors will cause serious performance degradation of the system. We reveal the details of the structures for (non-)multirate FIR filters, which are originally devised for the usage on the wireless communication link but are not limited to those specific applications. We also derive the general formulae of the numerical performance, under a given number representation format such as Q15, for the digital FIR filter. Unlike the case of FIR filters, the quantization of the states has the same amount of adverse effects to the quantization of coefficients in FIR filters. Finally, ASIC layouts and statistics of 1:4 interpolation FIR filter on a code division multiple access (CDMA) digital cellular communication link are included.

This brief provides a novel criterion for the analysis of convergence of states of an infinite impulse response (IIR) digital filter to a bounded region under the influence of composite effects of quantization and overflow nonlinearities. The developed criterion is less conservative in its approach in terms of analyzing stability than conventional methods and can be employed for implementation of an IIR filter on comparatively smaller hardware word-length than existing methods. The conventional approaches consider asymptotic stability of a filter with respect to the quantization noise; however, quantization in digital filters can result into bounded oscillation and lead to infeasibility of the asymptotic stability. Therefore, a less conservative stability analysis together with estimation of steady-state region of convergence for an IIR filter is provided. In addition, the conventional approaches, analyzing stability, and steady-state region of convergence, may not guarantee an overflow oscillation-free realization of a filter. Consequently, a condition for estimating the steady-state region of convergence (along with the filter stability) with an additional constraint that the filter’s state should not overflow in the bounded region has been derived. A comparative analysis with conventional methods is provided in simulation results.

This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

A pipelining method in lattice digital filters is introduced. This pipelining method is based on a constrained IIR (infinite impulse response) digital filter design method by which pipelined direct-form filters are designed. These direct-form filters are transformed to pipelined lattice digital filters. It is shown that the roundoff error and the number of multiply/add operations of the resulting pipelined lattice filters are smaller than those of the pipelined lattice filters obtained by applying look-ahead on direct-form nonpipelined digital filters. >

An efficient transformation method for the realization of a delayed multipath two-dimensional IIR (infinite impulse response) digital filter is presented. Although the structure does not give 100% multiprocessing efficiency, the maximum overall throughput improvement that can be achieved is high. The delayed multipath structure has been successfully applied to the realization of an FIR (finite impulse response) digital filter. In actual implementation, the method involves difficulty when applied directly to an IIR digital filter because of the inherent timing constraint in the recursive loop. With the transformation method, extra loop delay is allowed in the recursive part of the multipath structure. Consequently, the problem of inherent timing constraint in the recursive loop is solved. Furthermore, the transformation method is efficient in terms of computational complexity, throughput improvement, and multiprocessing efficiency.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital filter plays an important role in the advanced era of communication system. Digital filters basically provide high attenuation to the unwanted ones and offer very low or ideally zero attenuation to desired signal components when its impulse response is adjusted as per requirement. But the design of a digital filter satisfying all the required conditions is a challenging task. In this paper, design techniques of low pass FIR filters using Tukey window, Kaiser Window, and Gaussian window methods are presented. The magnitude and phase responses are demonstrated in the simulation section for the different design techniques of digital low pass FIR filters. From the simulation results, it is observed that for a longer length the FIR filter has a sharper cut-off FIR filter and a narrow transition band.