Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

The demand for cost-effective digital filters in near-sensor computing has aroused interest in stochastic computing (SC) as a promising alternative to traditional binary approaches. This study investigates in detail the error tolerance and hardware cost of SC-based digital filters of both the finite and infinite impulse response (FIR and IIR) types, focusing on their stochastic number generation and addition methods. We demonstrate that SC filters need only about half the area and power of binary designs under error-free conditions, though with a slight reduction of accuracy. Furthermore, these filters exhibit strong error resilience, with only 4X and 6X performance degradation under a 3% bit-flip rate, significantly outperforming their binary (non-SC) counterparts. We also compare the error tolerance of SC filters against binary filters equipped with triple modular redundancy (TMR). Our results indicate that for FIR filters, SC-based designs remain far more error-tolerant than binary FIR filters with TMR. However, in the IIR case, the binary designs with TMR outperform SC-based IIR filters at higher error rates. These findings highlight the possible trade-offs between SC and binary implementations, with SC offering more robust error tolerance, significant area and power savings and manageable accuracy trade-offs in most cases. This work also underscores SC’s potential as an efficient, resilient approach for low-cost digital filtering in edge devices and near-sensor computing applications.

Sigma-Delta modulators (SDMs) are capable of shaping the quantization noise out of a specific frequency band defined by their noise transfer function (NTF). A single-bit output SDM pose further advantages in applications that would typically require a multi-bit DAC, since then only a single-bit DAC is required, which is much easier to design and is inherently linear in comparison to a multi-bit one. Look-ahead SDMs have been proposed to enhance the signal-to-noise-and-distortion-ratio (SNDR) and the output bandwidth of conventional single-bit SDMs. Multi-Step Look-Ahead sigma-delta modulators (MSLA SDMs) further reduce the hardware complexity required for the implementation of typical look-ahead SDMs while maintaining their performance advantages. In this work the architecture and the benefits of the MSLA SDMs are showcased. Finally the advantages of the MSLA SDMs over single-bit conventional ones are demonstrated and several hardware implementation choices for design optimization are discussed.

Max & min architectures for stochastic computing (SC) are introduced. Their key characteristic is the utilization of an accumulator to store the signed difference between the two inputs, without randomizing sources. This property results in fast-converging and highly accurate computations using short sequence lengths, improving on the latency–accuracy tradeoff of existing SC max–min architectures. The operation of the proposed architectures is modeled using Markov Chains, resulting in in-depth analysis, the derivation of their statistical properties, and guidelines for selecting the register’s size to achieve overall design optimization. The computational accuracy and the hardware requirements of the proposed architectures are compared to those of existing ones in the SC literature, using MATLAB and Synopsys Tools. The efficacy of the proposed architectures is demonstrated by realizing a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3 \times 3$ </tex-math></inline-formula> median filter and using it in an image processing application.

Digital switching-mode power amplifiers (PA) based on bit-stream modulations such as Delta Sigma Modulations (DSM) have been studied as a potential solution to overcome the trade-off between the power efficiency and the signal linearity of RF PAs. FIR filtering has been introduced to suppress the quantization noise near signal band for those transmitters based on a combination of multiple power amplifiers. In this paper, the Channelized Active Noise Elimination (CANE) technique is proposed to implement the FIR filtering concept into the Envelope Delta Sigma Modulation (EDSM) scheme so that the low pass characteristics of the FIR filter is upconverted carrier to form a band pass filter. The advantage of CANE comparing to conventional FIR filtering is its small bandwidth, low sampling rate requirement and arbitrary carrier frequency and filter bandwidth selections. Simulation results are presented to demonstrate the effectiveness of the proposed approach.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

Bitstream Modulated transmitters based on Delta Sigma Modulation have been proved to be promising for efficient amplification of non-constant envelope signal. Such transmitters preserve signal linearity by converting the signal to binary envelope and shaping the quantization noise out of signal band. To further suppress the noise near the in band signal that is left from noise shaping, active FIR filter structure consisting of multiple identical amplifier units is proposed. In this paper, the Channelized Active Noise Elimination (CANE) technique is employed to create an effective band-pass FIR filter by delaying, up-converting the baseband signal and then combining them in RF. A special power combining network is designed to maintain the overall PA efficiency while the noise power is suppressed. An S-band transmitter prototype with 2-channels has been built and tested. The results demonstrated that the CANE technique can achieve filtering with software reconfigured flexibility while maintaining the power efficiency.

In this Paper, a fractional-N frequency synthesizer fabricated in a 0.18µm process is designed for a FSK transceiver. The precision of the charge pump can be improved by exploiting the op amplifier. Based on capacitance multiplication technique, the area of loop filter is reduced. The fractional-N divider function is realized by the sigma delta modulator. FIR filter is designed in the input stage of sigma-delta modulator to avoid spectrum aliasing. The data of sigma delta modulator can be stably transmitted to programmable frequency divider without meta-stability. The minimum step of frequency is 28Hz with 30MHz reference clock. The measurement results show that the phase noise is −129.69dBc/Hz @1-MHz offset with centered frequency at 390MHz.

This paper introduces an algorithm of a frequency flexible Gabor filter based on stochastic computation. The stochastic Gabor filter provides area-efficient hardware implementation compared to a traditional implementation, but a spacial frequency of the stochastic Gabor filter is restricted by the number of states in an up-down counter used in hardware. In the proposed algorithm, a frequency is determined by two parameters: the number of states and a scaling factor to an input signal. As the input-signal range is scaled down from a stochastic-signal range of [−1∶1], a tentative frequency determined by the number of states is precisely controlled to synthesize a flexible frequency desired. The proposed stochastic Gabor filter is modelled and simulated in MATLAB that demonstrates a flexible frequency is synthesized, unlike the conventional method.

In this article, we describe a thermal sigma-delta converter implementation with thermoresistive sensor for temperature measurement. The sensor was integrated to a 1-bit, first order, sigma-delta modulator in the place of the integrator and sum blocks. Part of the modulator circuit was digitally implemented by a microcontroller, which was integrated to the analog circuit part and to the NTC thermoresistive sensor. A digital filter, formed by a second order Comb filter followed by a FIR filter, was used to obtain the estimated temperature.

We present a technique for the design of multiplierless FIR filters with canonic signed digit (CSD) coefficients based on higher order sigma-delta modulation with a CSD quantizer (/spl Sigma//spl Delta/-CSD). The CSD quantizer yields FIR filter coefficients quantized to sums of a few signed powers-of-two digits, eliminating the need for multiplication. The sigma-delta modulation moves the quantization error out of the band of interest into a frequency band where the increased error can be attenuated by a cascaded prefilter in a prefilter-equalizer structure, or be attenuated by a decimation filter in a multi-rate approach. The use of higher order sigma-delta modulation provides more flexibility in moving the quantization error than the previously proposed first-order modulation. We give lowpass and bandpass examples where the filters designed by the higher order modulation demonstrate substantial frequency characteristic improvement. An empirical design guideline to ensure the stability for the higher order /spl Sigma//spl Delta/-CSD modulation is also given in the paper.

In order to get a thorough understanding of the total digital silicon micro-gyroscope, a novel system-level model with details of both the sense and circuit is presented in this paper. Unlike the traditional structures of the digital part of the digital gyroscope, a structure with programmable delay units (PDUs) instead of DPLLs gives a brief and robust character of the whole system. And the PDUs coordinating with the FIR filter could lead to a removal of the IF filters of the sigma–delta DAC for feedback, which saves a lot of consumption. Two MASH sigma–delta ADCs are designed to convert the output of the charge–voltage converters to digital signals, which also bring a better stability. The ADCs achieve an SNR of 102.5 dB with a 10 kHz bandwidth. The stabilization of the closed drive mode has also been analyzed including how the noise caused by the quantization of the digital circuit is affecting the stabilization of both the amplitude and frequency of the driving signals. In the end, a final result of simulation of the gyroscope shows the correctness and accuracy of the whole model of the gyroscope.

The CIC filter is often used as a decimating filter to simultaneously reduce bandwidth and sample rate of the time series obtained at the output of a 1-bit Sigma-Delta con-verter. The conventional motivation for using the CIC is that the filtering is performed with only registers and adders, there being no multipliers in the CIC filter chain. We note that every FIR filter processing the output of a 1-bit sigma delta convert-er can also be implemented without multipliers. The CIC filter does not take advantage of the fact that the input samples are limited to two input levels. It is possible to design FIR filters using the two level input signal to form efficient multiply free filters that compare favorably with the CIC filter. We present here a partition of the filter and down sampling task into a cascade of a polyphase pre-filter that performs a first band-width and sample rate reduction without multiplies followed by a reduced sample rate CIC filter performing the second bandwidth and sample rate reduction. Operating the second filter as a CIC at a reduced output rate reduces its workload and the bit width required by its accumulators.

Uncertain components in the integrators of 2–1 Sigma–Delta modulators cannot eliminate the first stage quantization noise completely, and the signal-to-noise ratio in analogue-to-digital converters is not reduced perfectly either. In order to solve the matching problem, older filter designs based on convex optimization are mathematically complicated, computationally intensive and not so efficient in application. In this paper, we propose a design method based on curve fitting approximation for uncertain linearized model of the modulator which is simple in principle and practical in application. Simulation results show that the optimal filter has better performance on multiple validations when compared to other modulator filters.

Quantization effect has a great impact on Digital Signal Processing Applications. Coefficients quantization is one of the three types of quantization that influences a response of system including signal processing parts. Hardware implementation of FIR filters enforces designer to quantize the FIR filter coefficients, then a proper way of quantization is important. To reach this goal, they need to meet suitable quantized frequency response which has more similarity to frequency response of infinite precision FIR filter. In this paper a new algorithm is described to quantize the coefficients of different types of FIR filters regardless of their method of designing. Also the conventional cascade form of implementing the FIR filters is modified in order to reach the better result of quantization. Various FIR filters designed based on different design methods are analyzed in this paper. The implementation results show that these two methods lead to better quantized FIR filters as compared to other algorithms.

This paper presents the effect of digital filtering in a sigma-delta modulation (SDM) used in wireless communications. SDM is widely used in digital-to-analog conversion because it offers high signal to noise ratio and distortion rate and low power and costs. SDM uses oversampling and noise shaping in order to move quantization noise from the signal band end and to eliminate it through a low pass filtering process. A SDM based scheme was implemented in a wireless communications system. Simulations were performed for different oversampling rates, digital filter types and communications channels. Bit error rate (BER) was used to evaluate the performances of the system.