Compile-time program restructuring in multiprogrammed virtual memory systems

The authors propose an information management system providing distribution and persistency. By separating context from virtual address space, the system has a unified approach for both distribution and persistency. The former is achieved by moving contents between sites and the latter by moving contents between virtual address space and persistent storage. Contents include any information including data, program, and even the state of execution of a program. Contents are stored persistently in a logical space termed the distributed shared repository (DSR). A programming model for the DSR is proposed. Using the model, persistency, fine-grain mobility of information, and the passing of various distributed parameters can be obtained. The implementation anti experimental performance of the system are also presented. >

No abstract available.

Memory-centric computing demands careful organization of the virtual address space, but traditional methods for doing so are inflexible and inefficient. If an application wishes to address larger physical memory than virtual address bits allow, if it wishes to maintain pointer-based data structures beyond process lifetimes, or if it wishes to share large amounts of memory across simultaneously executing processes, legacy interfaces for managing the address space are cumbersome and often incur excessive overheads. We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch between multiple virtual address spaces. Our work enables data-centric applications to utilize vast physical memory beyond the virtual range, represent persistent pointer-rich data structures without special pointer representations, and share large amounts of memory between processes efficiently.

Virtual memory system multiplexes the single physical memory for multiple running processes with two centralized resources, i.e., virtual memory space and page table hierarchy. However, for multithreaded applications running a single address space, current centralized VM system design encounters severe scalability bottlenecks and significantly impedes the application speedup increment on many-core systems. This paper proposes a novel VM system called MedusaVM to scale VM system to many cores. To this end, MedusaVM partitions the global virtual memory space and page table tree in a memory-efficient way, eliminating performance interference and lock contention between cores. Moreover, MedusaVM also provides a traditional shared memory interface for multithreaded applications.

Virtual machine introspection (VMI) is a technique for the external monitoring of virtual machines. Through previous work, it became apparent that VMI can contribute to the security of distributed systems and cloud architectures by facilitating stealthy intrusion detection, malware analysis, and digital forensics. The main shortcomings of active VMI-based approaches such as program tracing or process injection in production environments result from the side effects of writing to virtual address spaces and the parallel execution of shared main memory on multiple processor cores. In this paper, we present RapidVMI, a framework for active virtual machine introspection that enables fine-grained, multi-core aware VMI-based memory access on virtual address spaces. It was built to overcome the outlined shortcomings of existing VMI solutions and facilitate the development of introspection applications as if they run in the monitored virtual machine itself. Furthermore, we demonstrate that hypervisor support for this concept improves introspection performance in prevalent virtual machine tracing applications considerably up to 98 times.

Mobile ad hoc networks (MANETs) are networks with self-organizing capabilities and without a fixed infrastructure. Wireless nodes communicate among themselves using multi-hop radio relaying, without requiring the packets to pass through a central access point or a base station. Routing is a function of speed and stability with which the nodes are able to acquire addresses. Efficient routing forms the basis of a fast and reliable communication network. In a highly mobile and infrastructure-less scenario, pre-configuration of addresses is not possible. Therefore node addresses need to be configured dynamically with minimum delay and packet loss. The main task of an address auto-configuration protocol is to manage the resource address space. It must be able to select, allocate, and assign a unique network address to an un-configured node. This paper proposes a new address auto-configuration protocol for mobile ad hoc networks. The scheme uses virtual address space for addressing new nodes joining a network. The aim is to map one point from virtual address sheet to exactly one new node. The reason for using the term "virtual" is that the whole corresponding address space is a 2D flat sheet and each point of this sheet is virtually mapped to a node in MANET. The protocol uses coordinate values for generating addresses.

With the advent of the 64-bit microprocessor, the virtual address space supported by a workstation will be large enough to permit the use of a single shared address space spanning a network of workstations as the primary abstraction provided by a distributed operating system. In such a system, built upon a software distributed shared memory, the programmer has considerable flexibility when choosing a mechanism for interprocess communication. This flexibility permits the programmer to make a case-by-case choice between simplicity and performance when both goals are not simultaneously achievable. With the inclusion of mechanisms supporting protection and fault tolerance, it is believed that such a system can provide the advantages of conventional message-based distributed operating systems, in addition to several other benefits e.g. easy sharing of complex data structures between processes, transparent replication of server functions, and a uniform interface for all communication. >

Chapter 6 - Secondary Storage

With the rapidly growing demands for large capacity main memory in server systems and embedded systems, current DRAM-only approach is hitting the limit due to DRAM's capacity scaling issue and significant background power. With the emergence of new non-volatile memories, or storage-class memories (SCMs), we can now explore low power, high capacity memory subsystem by redesigning virtual memory system to be SCM-aware. Most research on virtual memory system design has focused on minimizing page fault frequency due to slow data transfers using storage such as HDD/SSD as virtual memory swap device. However with an SCM-based swap device, its near-DRAM access latency has potential for reducing requisite DRAM size by aggressively evicting pages from DRAM to SCM without sacrificing performance, and thus reducing background power by powering off the freed DRAM space for low power. To select an optimal SCM from among the many candidate SCM technologies, the impact of SCM characteristics was evaluated using full-system simulation. Results show that utilizing SCM with low access latency and low write energy can lead to significant potential reduction of memory subsystem energy by up to 83%, while maintaining performance degradation within acceptable range.

In the effort for exascale performance, current High-Performance Computing (HPC) systems need to be improved. Simple hardware scaling is not a feasible solution due to the increasing utility costs and power consumption limitations. Hence, apart from improvements in implementation technology, what is needed is to refine the HPC application development flow as well as the system architecture of future HPC systems. ECOSCALE tackles precisely these challenges by proposing a scalable programming environment and architecture, aiming to substantially reduce energy consumption as well as data traffic and latency. Furthermore, ECOSCALE introduces a novel heterogeneous energy-efficient hierarchical architecture, as well as a hybrid many-core+OpenCL programming environment and runtime system. The ECOSCALE approach is hierarchical and is expected to scale well by partitioning the physical system into multiple independent Workers. Workers are interconnected in a tree-like fashion and define a contiguous global address space that can be viewed either as a set of partitions in a Partitioned Global Address Space (PGAS), or as a set of nodes hierarchically interconnected via an MPI-like protocol. To further increase energy efficiency, as well as to provide resilience, the Workers employ reconfigurable accelerators mapped onto the virtual address space by utilising a dual-stage system memory management unit with coherent memory access. The architecture supports shared partitioned reconfigurable resources accessed by any Worker in a PGAS partition, as well as automated hardware synthesis of these resources from an OpenCL-based programming model.

A Dual-mode baseband (W-CDMA/HSDPA and GSM/GPRS/EDGE) and multimedia application processor SoC is described. The SoC fabricated in triple-Vth 65nm CMOS has 3 CPU cores and 20 separate power domains to achieve both high performance and low power. The SoC adopts the Partial Clock Activation scheme that reduces power by 42% for long-time music replay. The IP-MMU is introduced to reduce maximum memory footprint by 43MB, sharing external memory among CPUs and HW-IPs using virtual address space that enables reuse of physically fragmented memory.

An archiving model for a hierarchical information storage environment

Sprite is an operating system being designed for a network of powerful personal workstations. A virtual memory system has been designed for Sprite that currently runs on the Sun architecture. This virtual memory system has several important features. First, it allows processes to share memory. Second, it allows all of the physical pages of memory to be in use at the same time; that is, no pool of free pages is required. Third, it performs remote paging. Finally, it speeds program startup by using free memory as a cache for recently-used programs.

Exploring new electrolyte materials is important to comprehend high performance secondary charge storage devices for effective utilization of renewable energy. Ionic liquids with broad electrochemical voltage window and wide range of thermal stability are prospective materials for the same. As an improved version of this class of materials, we report herein, on the synthesis of novel pyrrolidinium based ionic liquid tethered nanoparticle hybrid electrolytes and compared their conductivity and electrochemical cycling behaviors. Hybrid electrolytes are prepared by covalently grafting N-Methyl-N-propylpyrrolidinium bis(trifluoromethanesulfonyl) imide to the surfaces of pre-synthesized TiO2 nanoparticles at three different core volume fractions, ranging from 0.11 to 0.46. Uniform dispersion of the core nanoparticle within the matrix of the electrolytes improves their mechanical properties. With increasing core volume fractions, the electrical conductivity slightly decreases due to increasing viscosity. Nevertheless, nanoparticle grafting significantly improves the electrochemical performance of the electrolytes. The electrolytes show very good capacitance retentivity (>90%) and long-term cycling stability above room temperature even at the lowest grafting density within symmetric stainless steel electrodes. Impressive room temperature electrochemical performance of these materials within symmetric supercapacitor cell containing CMS graphite as electrodes further demonstrates the applicability of these hybrid materials as promising electrolytes for secondary charge storage devices.

In Memory Computing is moving data into dynamic memory which is traditionally stored in secondary storage devices. In this paper we try to improve the capability of Java Virtual Machine (JVM) to process large data collections/application by pertinence of In-Memory Computing concepts. It helps JVM/processor to process huge data sets efficiently due to high-speed access and reduction of latency of slow secondary storage devices. It is implemented by providing more dynamic memory to JVM or by the implementation of In Memory Database concepts. In this paper we correlate Actual machine with JVM and try to improve ability of JVM to process large data collections by eliminating disk access and replacing Database with JAVA Collections in the Model Layer hence using `in memory' concepts, Henceforth a high performance system is designed.