Complexity classifications for different equivalence and audit problems for Boolean circuits

Boolean function is one of the most fundamental computation models in theoretical computer science. The two most common representations of Boolean functions are Fourier transform and real polynomial form. Applying analytic tools under these representations to the study Boolean functions has led to fruitful research in many areas such as complexity theory, learning theory, inapproximability, pseudorandomness, metric embedding, property testing, threshold phenomena, social choice, etc. In this thesis, we focus on \emph{sparse representations} of Boolean function in both Fourier transform and polynomial form, and obtain the following new results. A classical result of Rothschild and van Lint asserts that if every non-zero Fourier coefficient of a Boolean function $f$ over $\mathbb{F}_2^{n}$ has the same absolute value, namely $|\hat{f}(\alpha)|=1/2^k$ for every $\alpha$ in the Fourier support of $f$, then $f$ must be the indicator function of some affine subspace of dimension $n-k$. Here we slightly generalize their result, and show that Boolean functions whose Fourier coefficients take values in the set $\{-2/2^k, -1/2^k, 0, 1/2^k, 2/2^k\}$ are indicator functions of two disjoint affine subspaces of dimension $n-k$ or four disjoint affine subspaces of dimension $n-k-1$. Our main technical tools are results from additive combinatorics which offer tight bounds on the affine span size of a subset of $\mathbb{F}_2^{n}$ when the doubling constant of the subset is small. For polynomial representation of Boolean function, we study the distribution of the number of non-zero coefficients of \emph{random} Boolean functions. For a random Boolean function $f:\{0,1\}^n\rightarrow \{0,1\}$, i.e., a function whose value at each point on the Boolean cube is chosen independently and uniformly at random from $\{0,1\}$, in real polynomial representation, we give several bounds and concentration results about the distribution of the sparsity of $f$.

We consider three representations of a Boolean function, two of them in the real field and one in a Galois field modulo-2. By using these representations, an arbitrary Boolean function of n variables can always be expanded as a power series on the Boolean variables cut off to the n-th degree (n-form). Such representations are particularly useful for a unified treatment of the dynamics of a net of switching elements.

Symmetric polynomials over [formula omitted] and simultaneous communication protocols

Ordered Kronecker functional decision diagrams (OKFDD's) are a data structure for efficient representation and manipulation of Boolean functions. OKFDD's are a generalization of ordered binary decision diagrams (OBDD)s) and ordered functional decision diagrams and thus combine the advantages of both. In this paper, basic properties of OKFDD's and their efficient representation and manipulation are given. Starting with elementary manipulation algorithms, we present methods for the construction of small OKFDD's. Our approach is based on dynamic variable ordering and decomposition-type choice. For changing the decomposition type, we use an efficient reordering-based method. We briefly discuss the implementation of PUMA, an OKFDD package, which was used in all our experiments. These experiments demonstrate the quality of our methods in comparison to sifting and interleaving for OBDD's.

The article considers the representation of Boolean functions in the form of decision trees. It presents the bounds on average time complexity of decision trees for all classes of Boolean functions that are closed over substitution, and the insertion and deletion of unessential variables (the structure of these classes is described in the book by Jablonsky, Gavrilov and Kudriavtzev [5]. The obtained results are compared with the results developed by Moshkov in [6] that describe the worst case time complexity of decision trees.

Worst case examples for operations on OBDDs

Due to upscaling of digital systems, the development of efficient representations and manipulating algorithms of Boolean functions is becoming increasingly important. This paper considers the representation by the disjoint disjunctive form from representations of Boolean functions, and describes the properties, characteristics and manipulating algorithms. Conventionally used sharp operation and disjoint sharp operation are made more efficient for the algorithm which generates disjoint disjunctive forms. Moreover, a binary tree method is proposed as a method which generates disjoint disjunctive forms of positive and negative functions simultaneously. This binary tree method is also very powerful as a method to obtain negation of logical formulas, and is five to ten times faster than the conventional one using disjoint sharp operation in a case of 10‐variable function. Also, for the problem of number of product terms, which is generally regarded as a shortcoming of the disjoint disjunctive form, we conduct further studies by considering the simplest disjoint disjunctive form. Moreover, we show a unique negation algorithm as an example of using the properties of the disjoint disjunctive form more aggressively.

Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular representations, such as CNF, DNF, circuits and ROBDDs [4], offer different advantages and are preferred for different tasks. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. Our work addresses the construction of ROBDDs that represent outputs of a given Boolean circuit. It is used in synthesis and verification. Earlier works (Fujita, Fujisawa, and Kawato, 1988. Malik et al., 1988.) proposed ordering circuit inputs and gates by graph traversals. We contribute orderings based on circuit partitioning and placement, leveraging the progress in recursive bisection and multi-level min-cut partitioning achieved in late 1990s. Our empirical results show that the proposed orderings based on circuit partitioning and placement are more successful than straightforward DFS and BFS, as well as related heuristics.

Non-cancellative Boolean circuits: A generalization of monotone boolean circuits

Optimal ordered binary decision diagrams for read-once formulas

A language ABAL (Auburn Boolean Algebra Language) is described in this paper that permits machine representation and manipulation of Boolean functions. Functions may be specified in algebraic form or as lists of minterms or maxterms. Types of operations available in the language include functional form changes, simplification rules, prime implicant or prime implicate generation, functional minimization, functional combinations using Boolean operators, and truth table generation. ABAL is written in Basic-Plus for execution on a DEC PDP 11/40 RSTS/E System.

The Stochastic Boolean Function Evaluation problem for symmetric Boolean functions

Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.

Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.

Loading classical data into quantum registers is one of the most important primitives of quantum computing. While the complexity of preparing a generic quantum state is exponential in the number of qubits, in many practical tasks the state to prepare has a certain structure that allows for faster preparation. In this paper, we consider quantum states that can be efficiently represented by (reduced) decision diagrams, a versatile data structure for the representation and analysis of Boolean functions. We design an algorithm that utilizes the structure of decision diagrams to prepare their associated quantum states. Our algorithm has a circuit complexity that is linear in the number of paths in the decision diagram. Numerical experiments show that our algorithm reduces the circuit complexity by up to 31.85% compared to the state-of-the-art algorithm, when preparing generic $n$-qubit states with ${n}^{3}$ nonzero amplitudes. Additionally, for states with sparse decision diagrams, including the initial state of the quantum Byzantine agreement protocol, our algorithm reduces the number of controlled-nots by 86.61--99.9%.