Non-cancellative Boolean circuits: A generalization of monotone boolean circuits

In this chapter we apply communication complexity to obtain methods for proving lower bounds on the complexity measures of VLSI circuits. A VLSI circuit is a more powerful computing model than the Boolean circuit model. While the gates (processors) of VLSI circuits are as simple as the gates of Boolean circuits, the communication structure (the graph describing the connections between processors) of VLSI circuits may contain cycles. This requires that a computation of a VLSI circuit be considered as an alternating sequence of synchronized steps C1, D1, C2, D2 ..., where Ci are communication steps and Di are working steps. In every communication step each directed edge (p 1, p 2) (communication link) transfers a binary value as the output of the processor pl to the processor p2. In every working step each node (processor) of the VLSI circuit computes outputs according to the values of its inputs. This contrasts to the Boolean circuits, where each processor and each directed edge were at most once active in the whole computation on an input. The main complexity measures of the VLSI circuit model are layout area A and time T (the number of working steps) . Since many computing problems may be solved with small area A if one allows a large time T and with small T if one allows relatively large A, one prefers to consider tradeoffs of complexity measures like A. T, A• T2 in order to objectify the measurement of the hardness of computing problems.

Cyclic Boolean circuits

Boolean circuits versus arithmetic circuits

We compare the measures of sequential time modelled using Turing machines and of parallel size modelled using Boolean circuits. This is done by constructing oracles which show certain relationships between complexity classes. An oracle B is shown for which Δ2P,B has 2n+o(n) size circuits relative to B. On the other hand, we give a C so that PC does not, for any k, have size nk circuits relative to C and yet NPC ≡ coNPC. These techniques can be combined to yield a D relative to which PD has 2n + o(n) size circuits but RD does not have size nk circuits for any k.

On the Circuit Complexity of Sigmoid Feedforward Neural Networks

We consider the extension of Boolean circuits to quantified Boolean circuits by adding universal and existential quantifier nodes with semantics adopted from quantified Boolean formulas (\(\mbox{\rm QBF}\)). The concept allows not only prenex representations of the form \(\forall x_{1}\exists y_{1}...\forall x_{n}\exists y_{n}\ c\) where c is an ordinary Boolean circuit with inputs x 1,...,x n ,y 1,...,y n . We also consider more general non-prenex normal forms with quantifiers inside the circuit as in non-prenex \(\mbox{\rm QBF}\), including circuits in which an input variable may occur both free and bound. We discuss the expressive power of these classes of circuits and establish polynomial-time equivalence-preserving transformations between many of them. Additional polynomial-time transformations show that various classes of quantified circuits have the same expressive power as quantified Boolean formulas and Boolean functions represented as finite sequences of nested definitions (\(\mbox{\rm NBF}\)). In particular, universal quantification can be simulated efficiently by circuits containing only existential quantifiers if overlapping scopes of variables are allowed.KeywordsNormal FormBoolean FunctionFree VariableExpressive PowerOutgoing EdgeThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Secure Multi-party Computation (SMC) protocols are exploited to perform collaborative computation of a function between two or more parties while keeping the privacy of the private inputs and sharing the computed result only. The Garbled Circuit (GC) protocol, proposed by Yao, is one of the possible approaches to solve the SMC problem, based on the evaluation of the Boolean Circuit representing the given function. Recently, the question to improve efficiency in secure multi-party computation has gained much interest. One of the proposed techniques to increase the efficiency of the GC protocol is based on the reduction of the number of non-XOR gates in the Boolean circuit, since the evaluation of XOR gates have no cost for the execution of the whole protocol. The aim of this work is to define a post-processing procedure that, given an optimized GC, decreases the number of non-XOR gates by transforming some parts of the circuit. The strategy is based on the fact that some gates behave as XORs apart from one output and then, if that input never occurs, those gates can be replaced by a XOR without changing the output of the overall network. The technique we propose is based on the analysis of the GC by using Ordered Binary Decision Diagrams (OBDD) representation. We present the application of our technique to some standard circuits to show the effectiveness of our proposal.

In several previous works the construction of a computationally hard function with respect to a certain class of algorithms or Boolean circuits has been used to derive small pseudo-random spaces. In this paper, we revert this connection by presenting two new direct relations between the efficient construction of pseudo-random (both two-sided and one-sided) sets for Boolean affine spaces and the explicit construction of Boolean functions having hard branching program complexityIn the case of 1-read branching programs (1-Br.Pr.), we show that the construction of non trivial (i.e. of cardinality 2o(n)) discrepancy sets (i.e. two-sided pseudo-random sets) for Boolean affine spaces of dimension greater than n/2 yield a set of explicit Boolean functions having very hard 1-Br.Pr. size. By combining the best known construction of ∈-biased sample spaces for linear tests and a simple “Reduction” Lemma, we derive the required discrepancy set and obtain a Boolean function in P having 1-Br.Pr. size not smaller than \(2^{n - O\left( {log^2 n} \right)} \) and a Boolean function in DTIME\(\left( {2^{O\left( {log^2 n} \right)} } \right)\) having 1-Br.Pr. size not smaller than 2n-O(log n). The latter bound is optimal and both of them are exponential improvements over the best previously known lower bound that was \(2^{n - 3n^{1/2} } \)[21].As for non deterministic syntactic k-read branching programs (k-Br.Pr.), we introduce a new method to derive explicit, exponential lower bounds that involves the construction of hitting sets (one-sided pseudo-random sets) for affine spaces of dimension o(n=2). Using an appropriate “orthogonal” representation of small Boolean affine spaces, we efficiently construct these hitting sets thus obtaining an explicit Boolean function in P that has k-Br.Pr. size not smaller than \(2^{n^{1 - o\left( 1 \right)} } \) for any \(k = o\left( {\frac{{\log n}}{{\log \log n}}} \right)\). This improves over the previous best known lower bounds given in [8,11,17] for some range of k

For a d-ary Boolean function Φ: {0, 1}d → {0, 1} and an assignment to its variables x = (x1, x2, . . . , xd) we consider the problem of finding those subsets of the variables that are sufficient to determine the function value with a given probability δ. This is motivated by the task of interpreting predictions of binary classifiers described as Boolean circuits, which can be seen as special cases of neural networks. We show that the problem of deciding whether such subsets of relevant variables of limited size k ≤ d exist is complete for the complexity class NPPP and thus, generally, unfeasible to solve. We then introduce a variant, in which it suffices to check whether a subset determines the function value with probability at least δ or at most δ − γ for 0 < γ < δ. This promise of a probability gap reduces the complexity to the class NPBPP. Finally, we show that finding the minimal set of relevant variables cannot be reasonably approximated, i.e. with an approximation factor d1−α for α > 0, by a polynomial time algorithm unless P = NP. This holds even with the promise of a probability gap.

We study Boolean circuits as a representation of Boolean functions and consider different equivalence, audit, and enumeration problems. For a number of restricted sets of gate types (bases) we obtain efficient algorithms, while for all other gate types we show these problems are at least NP-hard.

Lower bounds on the area complexity of Boolean circuits

We examine the power of nondeterministic finite automata with acceptance of an input word defined by a so called leaf language, i. e., a condition on the sequence of leaves in the automaton's computation tree. We study leaf languages either taken from one of the classes of the Chomsky hierarchy, or taken from a time- or space-bounded complexity class. We contrast the obtained results with those known for leaf languages for Turing machines and Boolean circuits.

In this chapter we present the foundations of parallel computing. We discuss Amdahl’s Law Gustafson’s Law the NC complexity class and Boolean circuits. We present pthreads, the POSIX thread API for expressing parallel programs. The multi-faceted parallelism present in the Cell architecture is introduced.We also briefly discuss OpenMP. This chapter also includes a list of things to watch out for when writing programs for the Cell.

We define the counting classes NC/sup 1/, GapNC/sup 1/ PNC/sup 1/ and C/sub =/NC/sup 1/. We prove that Boolean circuits, algebraic circuits, programs over nondeterministic finite automata, and programs over constant integer matrices yield equivalent definitions of the latter three classes. We investigate closure properties. We observe that NC/sup 1//spl sube/L and that C/sub =/NC/sup 1//spl sube/L. Then we exploit our finite automaton model and extend the padding techniques used to investigate leaf languages. Finally, we draw some consequences from the resulting body of leaf language characterizations of complexity classes, including the unconditional separation of ACC/sup 0/ from MOD-PH as well as that of TC/sup 0/ from the counting hierarchy. Moreover we obtain that dlogtime-uniformity and logspace-uniformity for AC/sup 0/ coincide if and only if the polynomial time hierarchy equals PSPACE.

Due to the non- intuitive nature of Quantum algorithms, it becomes difficult for a classically trained person to efficiently construct new ones. So rather than designing new algorithms manually, lately, Genetic algorithms (GA) are being implemented for this purpose. GA is a technique to automatically solve a problem using principles of Darwinian evolution. This has been implemented to explore the possibility of evolving an n-qubit circuit when the circuit matrix has been provided using a set of single, two and three qubit gates. Using a variable length population and universal stochastic selection procedure, a number of possible solution circuits, with different number of gates can be obtained for the same input matrix during different runs of GA. The given algorithm has also been successfully implemented to obtain two and three qubit Boolean circuits using Quantum gates. The results demonstrate the effectiveness of the GA procedure even when the search spaces are large.