VLSI Circuits and Interconnection Networks

Non-cancellative Boolean circuits: A generalization of monotone boolean circuits

Floorplanning is a key step in the physical design of Very Large Scale Integrated (VLSI) circuits. It is a multi-objective combinatorial optimization and has been proved to be a NP-hard problem. To solve this problem, a coevolutionary multi-objective particle swarm optimization (CMOPSO) algorithm is proposed in this paper. The algorithm imports the concept of coevolutionary algorithm and elitist strategy into basic PSO algorithm, takes both the layout area and total interconnection wire length into consideration simultaneously. Experimental results showed the new algorithm can achieve a better performance.

Boolean circuits versus arithmetic circuits

Interconnection Networks are widely used in many applications such as parallel and massively parallel systems, industrial applications, VLSI circuits, electronic devices and telephone switches etc. The realization of data communication in parallel system is possible all the way through interconnection networks. The whole performance of the system depends on the type of interconnection networks used. Interconnection networks with embed ability by some other interconnection structure, high resilience, simple routing, constant node degree, and scalability are highly desirable. We had introduced Octagon-Cell Networks (OCN), in the past research, which is a new interconnection network. In this research, we introduce and prove the fundamental theorems for finding the optimal path length between any pair of source and destination nodes in Octagon-Cell Network of any depth. The basic objective of these theorems (excluding Horizontal and Vertical Moves) to calculate the optimal path length, is to check whether any intermediate node exists along the optimal path, for which its line number or serial number matches with the line number or the serial number of destination node respectively. We also introduce the theorems to find the total number of horizontal lines, which is the maximum line number of a node, as well the total number of vertical lines, which is the maximum serial number of a node in Octagon-Cell Network of any depth. The theorems are proved mathematically and are tested successfully on all possible cases.

Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.

With all of the salient features of hypercubes, the cube-connected cycles (CCC) structure is an attractive parallel computation network suited for very large scale integration (VLSI) implementation because of its layout regularity. Unfortunately, the classical CCC structure tends to suffer from considerable performance degradation in the presence of faults. The authors deal with a fault-tolerant CCC structure obtained by incorporating a spare PE in each cycle and by adding extra links among PE's to realize dimensional substitutes for failed PE's in the immediate lower dimension. A unique feature of this design lies in that a faulty PE and its laterally connected PE are always replaced at the same time by their immediate vertical successor pair, achieving pairwise substitution to elegantly maintain the rigid full CCC structure after faulty PE's arise. The proposed structure improves reliability substantially without incurring large overhead in layout area. This design is compared with earlier fault-tolerant CCC designs in terms of normalized reliability, which takes area overhead into account. An extension to this fault-tolerant structure is also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new class of switch-level logic circuits intended for modeling digital MOS VLSI circuits is presented. These circuits, which are called pseudo-Boolean, are composed of a single (voltage) source, connectors, switches, attenuators, and wells. The latter two devices are digital versions of resistors and capacitors, respectively, and may assume an arbitrary but finite number of different sizes. Signals are bidirectional, and are assigned a finite set of values of the form (v, s) where v corresponds to voltage level and s corresponds to electrical current or charge level (logical strength). It is shown that these signal values and the associated logical operations form a generalization of Boolean algebra called pseudo-Boolean or Heyting algebra. The analysis of pseudo- Boolean circuits using discrete counterparts of Kirchoff's current law and the superposition principle is discussed, as well as the application of pseudo-Boolean techniques to digital simulation.

Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme.

This chapter discusses about the behavior of Carbon Nanotube (CNT) different structures which can be used as interconnect in Very Large Scale (VLSI) circuits in nanoscale regime. Also interconnect challenges in VLSI circuits which lead to use CNT as interconnect instead of Cu, is reviewed. CNTs are classified into three main types including Single-walled Carbon Nanotube (SWCNT), CNT Bundle, and Multi-walled Carbon Nanotube (MWCNT). Because of extremely high quantum resistance of a SWCNT which is about 6.45 kΩ, rope or bundle of CNTs are used which consist of parallel CNTs in order to overcome the high delay time due to the high intrinsic (quantum) resistance. Also MWCNTs which consist of parallel shells, present much less delay time with respect to SWCNTs, for the application as interconnects. In this chapter, first a short discussion about interconnect challenges in VLSI circuits is presented. Then the repeater insertion technique for the delay reduction in the global interconnects will be studied. After that, the parameters and circuit model of a CNT will be discussed. Then a brief review about the different structures of CNT interconnects including CNT bundle and MWCNT will be presented. At the continuation, the time domain behavior of a CNT bundle interconnect in a driver-CNT bundle-load configuration will be discussed and analyzed. In this analysis, CNT bundle is modeled as a transmission line circuit model. At the end, a brief study of stability analysis in CNT interconnects will be presented.

Pipelined two-operand modular adder (TOMA) is one of basic components used in digital signal process- ing (DSP) systems that use the residue number system (RNS). Such modular adders are used in binary/residue and residue/binary converters, residue multipliers and scalers as well as within residue processing channels. The structure of pipelined TOMAs is usually obtained by in- serting an appropriate number of pipeline register layers within a nonpipelined TOMA structure. Hence the area of pipelined TOMAs is determined by the nonpipelined TOMA structure and by the total number of pipeline registers. In this paper we propose a new pipelined TOMA, that has a considerably smaller area and the attainable pipelining frequency comparable with other known pipelined TOMA structures. We perform comparisons of the area and pipe- lining frequency with TOMAs based on ripple carry adder (RCA), Hiasat TOMA and parallel-prefix adder (PPA) using the data from the very large scale of integration (VLSI) standard cell library. n m m m X X X with i m i x Z  . This mapping is the bijection and for X, Y  ZM and for i m i i y x Z  , , we have i m i i i y x z   ,where  denotes addition, subtraction or

Lower bounds on the area complexity of Boolean circuits

With continuous advances in radio-frequency (RF) mixed-signal very large scale integration (VLSI) technology, the creation of eddy currents in lossy multilayer substrates has made the already complicated interconnect analysis and modeling issue more challenging. To account for substrate losses, traditional electromagnetic methods are often computationally prohibitive for today's VLSI geometries. In this paper, an accurate and efficient interconnect modeling approach-the eddy-current-aware partial equivalent element circuit (EPEEC)-is proposed. Based on complex image theory, it extends the traditional partial equivalent element circuit (PEEC) model to simultaneously take multilayer substrate eddy-current losses and frequency-dependent effects into consideration. To accommodate even larger scale on-chip interconnect networks, EPEEC develops a new simulation program with integrated circuit emphasis (SPICE)-compatible reluctance extraction algorithm by applying sparsification in the inverse inductance domain with an extended window algorithm. Compared with several industry standard inductance and full-wave solvers, such as FastHenry and Sonnet, EPEEC demonstrates within 1.5% accuracy while providing over 100/spl times/ speedup.

Now a days as far as technology going to advances still some problem in VLSI interconnect. Cu interconnect is batter As compared with gold, silver Even though cu interconnect also major drawback because billion of transistor were integrating single chip. So Interconnect Delay is major problem. In this paper compares the Cu interconnect with CNT interconnect and performances parameter like power delay and power delay product were taken at Intermediate and global level with Different technology for analysis. from the Simulation, it found that CNT based interconnect is suited for high performances application .the simulation has done using T_Spices

Optimal algorithms for dissemination of information in generalized communication modes

The WK-recursive mesh and WK-pyramid networks are recursively-defined hierarchical interconnection networks with excellent properties which well idealize them as alternatives for mesh and traditional pyramid interconnection topologies. They have received much attention due to their favorable attributes such as small diameter, large connectivity, and high degree of scalability and expandability. In this paper, we deal with packagibility and layout area of these networks. These properties are of great importance in the implementation of interconnection networks on chips. We show that WK-recursive, mesh-pyramid and WK-pyramid networks can be laid out in an area of O(N2) which is the optimal area for VLSI layout of networks. Also, we obtained the number of tracks for laying nodes in a collinear model, where the chips are multi-layered.KeywordsVLSI layoutThompson grid modelMultilayer grid modelWK-recursiveWK-pyramidInterconnection networks