Pipelined Two-Operand Modular Adders

Design and implementation of area efficient EAIC modulo adder

Modular adders are fundamental arithmetic components that are employed in residue number system (RNS) based digital signal processing (DSP) systems. They are widely used in modular multipliers, residue to binary converters and in implementing other arithmetic operations such as scaling. In addition, increasing operating frequencies, as well as a growing demand for portable electronics, have brought power reduction to the forefront of modern design methodologies. Thus, the design of power efficient modular adders is of great significance if RNS circuits are to be utilized in future DSP systems. We propose a new modular adder that is based on the ELM addition algorithm. VLSI implementations using 0.13 /spl mu/m standard-cell technology show that the proposed architecture not only exhibits power efficiency, but also delay /spl times/ area efficiency when compared to existing modular adder designs in the literature.

Finite impulse response (FIR) digital filters are key components used in many digital signal processing (DSP) systems because of their linear phase, stability, fewer finite precision errors and regular structure. The real time realization of FIR filter with less hardware requirement and less latency has become very critical with increasing developments in very large scale integration (VLSI) technology. The objective of this paper to explore the current trends in the development of algorithms and architectures for memory based realization of FIR filters that are mainly concerned with reducing the overall area-delay-power complexities. The purpose of this study is to compare these architectures based on ROM size, delay and throughput. The results presented here would assist the researchers in the field of Digital Signal processing to select best architecture for an application based on requirements. New algorithms and architectures need to be developed to design area-delay-power-efficient FIR filters for various demanding DSP applications.

In this paper we have designed a novel dedicated low power 64 bit digital comparator. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI) designers. A Low Power 64-bit CMOS binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on power delay product. Modifications are done in existing 64-bit binary comparator design to improve the PDP of the circuit. Simulation of the proposed design is performed at 180 nm technology in Tanner EDA Tool.

High-speed multiplication is a fundamental requirement in modern computing systems, including applications in digital signal processing (DSP), artificial intelligence (AI), and cryptography. This paper presents an optimized 64-bit Dadda multiplier incorporating a Brent-Kung Adder (BKA) and 4:2 compressors to enhance speed and efficiency. The Dadda multiplier is widely recognized for its reduced number of reduction stages, significantly minimizing delay and hardware complexity. The integration of the Brent-Kung Adder, a parallel prefix adder with logarithmic delay, further improves performance by reducing carry propagation delay in the final addition stage. The proposed design is implemented in Verilog and synthesized on an FPGA to evaluate its efficiency in terms of delay, power consumption, and area utilization. A comparative analysis is conducted against 32-bit Dadda multipliers utilizing Ripple Carry Adder (RCA) and Carry Select Adder (CSLA), demonstrating that the 64-bit Dadda multiplier with BKA achieves superior speed while maintaining reasonable power and area efficiency. Simulation results reveal that the proposed design achieves a propagation delay of 28.228 ns, significantly lower than traditional approaches. The inclusion of 4:2 compressors further optimizes partial product reduction, ensuring a more efficient multiplication process. By leveraging an optimized reduction strategy and an efficient parallel prefix adder, this work provides a robust solution for real-time applications requiring high-speed arithmetic computations. The balance between speed, power, and hardware utilization makes this design a practical choice for applications demanding efficient multiplication operations.

The hallmark of the Rowan College of Engineering undergraduate program is to provide effective laboratory based instruction that illustrates important scientific concepts. This paper presents the results of an effort by the Department of Electrical and Computer Engineering at Rowan University to configure a novel method of teaching the junior level Communications (COMM), Digital Signal Processing (DSP) and Very Large Scale Integration (VLSI) courses under a common laboratory framework. These three courses are taken concurrently during the spring semester of the junior year. Twelve interdisciplinary experiments that cut across individual course boundaries and that integrate hands-on experience and software simulation are proposed. The first four experiments deal with the very basic concepts. The next four experiments expose the students to multimedia standards approved by industry. The last four experiments deal with various applications that link COMM, DSP and VLSI. Software is integrated with the experiments through MATLAB and SIMULINK, C/C++ and Mentor Graphics.

This paper presents the methods we used to achieve an exhaustive comparison of specific arithmetic operators and the result of this comparative study. The operators we were interested in are modular adders that can be used for Residue Number System (RNS) processors. RNS arithmetic provides an alternative way to produce highly effective multiplication and addition and are, therefore, of great interest for signal processing processors. As modular adders are at the root of any RNS processor, attention must be payed to their design. We expose three different existing designs for such adders and through the construction and use of generators that produce 0.35μ standard cell architectures, we synthesized those three designs for all odd moduli from 4 to 15 bits and measured their performance. Performance was measured after placement and routing of those operators providing precise results. The exhaustive data obtained let us compare those three designs based on size, speed or any combination of those two fore-mentioned factors. Eventually this study gives clues on choosing a specific modular adder for a given modulus and also for choosing the best candidates for a well balanced residue base (i.e. choosing a good set of moduli). Furthermore, it shows that the described parallel modular adder is generally the best choice.

In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital signal processing use these carry adders. The carry output of every finished adder stage is useful as a carry input to the one behind it. This procedure is continued until the last complete adder stage is reached. Each carry output bit in an entire adder is therefore rippled to the next stage. An exact (forward) carry adder be linked with the proposed structure to generate hybrid adders with tunable accuracy levels. The practical implementation of proposed model is carried out using Xilinx ISE Design Suite 13.4, showcasing its feasibility for real-world applications.

Floating-point arithmetic has various applications in the field of Science and Engineering. Specially, need of high precision floating-point multipliers is observed in Digital Signal Processing- like in filtering and transformations . High speed signal processing demands for high speed hardware. Though, various high level languages based implementations of floating-point multiplier are observed so far, but the hardware based implementation has still remained a bottleneck. With the development of Very Large Scale Integration (VLSI) technology, Field Programmable Gate Array (FPGA) has become the best candidate for implementing floating-point multipliers (due to their high integration density, low price, high performance and flexible applications). In this work, we have shown the implementation of IEEE-754 single precision floating-point multiplier on FPGA using carry-look ahead adder (for exponent addition). The multiplier may be used in adaptive filters for multiplying the fractional step size (mue) to update the filter weights. This paper also presents the comparative analysis of proposed design with Spartan 6 FPGA's built-in IPcore for floating-point multiplier. The results are compared in terms of recourse utilization, power consumption, observed delay, logic levels and maximum achieved frequency. It is shown that our design is better in terms of achieved frequency with a small increase in resource utilization.

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

Energy consumption in Digital Signal Processing (DSP) application is a vital parameter of consideration. Mostly DSP applications deplete power. Battery constraint is important in many mobiles, processors, and sensor-related devices. The major critical operations in DSP architecture are multiplication and addition. Multiplication process is performed using repetitive addition. Hence, adder is the basic component used in digital signal processor. DSP architecture is proposed with the energy-efficient goal. Traditional carry select adder contains ripple carry adder block is replaced by parallel prefix adder. By replacing that block and introducing folded tree, we can reduce power used by DSP processors. This architecture can be used in all power constrained DSP applications. In the existing system, folded tree is used in architecture to reduce the number of processing elements, and they used carry look-ahead adder to perform the internal processing element operations. In the proposed system, carry look-ahead adder is replaced by LFA and PA to harness the energy depleted in an application (e.g., DSP application). Power consumption is reduced by 12–15% as compared with the existing algorithms using Cyclone III (EP3C16F484C6).

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I & New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

The scaling operation, i.e. the division by a constant factor followed by rounding, is a commonly used technique for reducing the dynamic range in digital signal processing (DSP) systems. Usually, the constant is a power of two, and the implementation of the scaling is reduced to a right shift. This basic operation is not easily implementable in the residue number system (RNS) due to its non positional nature. A number of different algorithms have been presented in the literature for the RNS scaling. In this paper, several RNS dynamic reduction techniques have been analyzed and the selected one is applied to a polyphase filter bank. A comparison of the filter bank scaled with RNS to binary and binary to RNS conversions, and the RNS scaled implementation is presented. A reduction of area and power consumption of about 30% for the scaling block is obtained.

Low power design of VLSI c ircuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP).Multiplier has an important role in the DSPs.Without degrading the performance of the processor, low power parallel mult ipliers are needed to be design.Bypassing is the widely used technique in the DSPs when the input operand of the mult iplier is zero.A Row based Bypassing Multiplier with comp ressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed.The proposed bypassing mu ltip lier with co mpressor shows high performance and energy efficiency than Kuo mu ltiplier with Carry Save Adder (CSA) at the final RCA.

High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.