Pseudo-Boolean Logic Circuits

A metric characterization of (n+1)-terminal positive resistance networks is undertaken using concepts of distance geometry. Terminal weight numbers (TWN) and the network diameter are used in the characterization. Three structural constraints that must be obeyed by these quantities are stated. An interesting conclusion of the investigation is that Kirchoff's current law (KCL), by itself, does not suffice for a complete structural characterization and evaluation of an electrical network. It is shown that KCL must be combined with TWN for a complete structural network description.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Transmission lines form the backbone of power and communication networks, yet their behavior cannot be predicted by classical transmission line theory, which neglects thermal feedback and fractional-order dynamics. To address these limitations, we develop an advanced fractal-fractional electro-thermal model of a lossy transmission line to analyze voltage and current propagation under thermal feedback. The model is based on the fractal-fractional derivative in the sense of Caputo and integrates the effects of series resistance, inductance, conductance, and capacitance together with temperature-dependent feedback. The coupled governing equations are derived as fractal-fractional order partial differential equations based on Kirchoff's current law (KCL) and Kirchoff's voltage law (KVL). The equations are solved numerically using the local radial basis functions (LRBF) scheme, a meshfree numerical technique, to investigate the spatio-temporal profiles of voltage, current, and temperature. The numerical results demonstrate that higher resistance and conductance increase both the attenuation and heating, while increasing capacitance reduces voltage propagation but enhances the current propagation. Furthermore, fractional and fractal orders enrich the analysis by introducing memory and dispersive effects. Overall, this study offers a more realistic and predictive framework for evaluating lossy transmission systems, with direct implications for improving reliability, thermal management, and performance in modern electrical and communication infrastructures.

In this paper, the impact of gate induced drain leakage (GIDL) on overall leakage of submicron VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down CMOS devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35 /spl mu/m CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield.

Preface. 1. The Physics of Electricity. 1.1 Basic Quantities. 1.1.1 Introduction. 1.1.2 Charge. 1.1.3 Potential or Voltage. 1.1.4 Ground. 1.1.5 Conductivity. 1.1.6 Current. 1.2 Ohm's law. 1.2.1 Resistance. 1.2.2 Conductance. 1.2.3 Insulation. 1.3 Circuit Fundamentals. 1.3.1 Static Charge. 1.3.2 Electric Circuits. 1.3.3 Voltage Drop. 1.3.4 Electric Shock. 1.4 Resistive Heating. 1.4.1 Calculating Resistive Heating. 1.4.2 Transmission Voltage and Resistive Losses. 1.5 Electric and Magnetic Fields. 1.5.1 The Field as a Concept. 1.5.2 Electric Fields. 1.5.3 Magnetic Fields. 1.5.4 Electromagnetic Induction. 1.5.5 Electromagnetic Fields and Health Effects. 1.5.6 Electromagnetic Radiation. 2. Basic Circuit Analysis. 2.1 Modeling Circuits. 2.2 Series and Parallel Circuits. 2.2.1 Resistance in Series. 2.2.2 Resistance in Parallel. 2.2.3 Network Reduction. 2.2.4 Practical Aspects. 2.3 Kirchhoff's Laws. 2.3.1 Kirchhoff's Voltage Law. 2.3.2 Kirchhoff's Current Law. 2.3.3 Application to Simple Circuits. 2.3.4 The Superposition Principle. 2.4 Magnetic Circuits. 3. AC Power. 3.1 Alternating Current and Voltage. 3.1.1 Historical Notes. 3.1.2 Mathematical Description. 3.1.3 The rms Value. 3.2 Reactance. 3.2.1 Inductance. 3.2.2 Capacitance. 3.2.3 Impedance. 3.2.4 Admittance. 3.3 Power. 3.3.1 Definition of Electric Power. 3.3.2 Complex Power. 3.3.3 The Significance of Reactive Power. 3.4 Phasor Notation. 3.4.1 Phasors as Graphics. 3.4.2 Phasors as Exponentials. 3.4.3 Operations with Phasors. 4. Generators. 4.1 The Simple Generator. 4.2 The Synchronous Generator. 4.2.1 Basic Components and Functioning. 4.2.2 Other Design Aspects. 4.3 Operational Control of Synchronous Generators. 4.3.1 Single Generator: Real Power. 4.3.2 Single Generator: Reactive Power. 4.3.3 Multiple Generators: Real Power. 4.3.4 Multiple Generators: Reactive Power. 4.4 Operating Limits. 4.5 The Induction Generator. 4.5.1 General Characteristics. 4.5.2 Electromagnetic Characteristics. 4.6 Inverters. 5. Loads. 5.1 Resistive Loads. 5.2 Motors. 5.3 Electronic Devices. 5.4 Load from the System Perspective. 5.4.1 Coincident and Noncoincident Demand. 5.4.2 Load Profiles and Load Duration Curve. 5.5 Single- and Multiphase Connections. 6. Transmission and Distribution. 6.1 System Structure. 6.1.1 Historical Notes. 6.1.2 Structural Features. 6.1.3 Sample Diagram. 6.1.4 Topology. 6.1.5 Loop Flow. 6.1.6 Stations and Substations. 6.1.7 Reconfiguring the System. 6.2 Three-Phase Transmission. 6.2.1 Rationale for Three Phases. 6.2.2 Balancing Loads. 6.2.3 Delta and Wye Connections. 6.2.4 Per-Phase Analysis. 6.2.5 Three-Phase Power. 6.2.6 D.C. Transmission. 6.3 Transformers. 6.3.1 General Properties. 6.3.2 Transformer Heating. 6.3.3 Delta and Wye Transformers. 6.4 Characteristics of Power Lines. 6.4.1 Conductors. 6.4.2 Towers, Insulators, and Other Components. 6.5 Loading. 6.5.1 Thermal Limits. 6.5.2 Stability Limit. 6.6 Voltage Control. 6.7 Protection. 6.7.1 Basics of Protection and Protective Devices. 6.7.2 Protection Coordination. 7. Power Flow Analysis. 7.1 Introduction. 7.2 The Power Flow Problem. 7.2.1 Network Representation. 7.2.2 Choice of Variables. 7.2.3 Types of Buses. 7.2.4 Variables for Balancing Real Power. 7.2.5 Variables for Balancing Reactive Power. 7.2.6 The Slack Bus. 7.2.7 Summary of Variables. 7.3 Example with Interpretation of Results. 7.3.1 Six-Bus Example. 7.3.2 Tweaking the Case. 7.3.3 Conceptualizing Power Flow. 7.4 Power Flow Equations and Solution Methods. 7.4.1 Derivation of Power Flow Equations. 7.4.2 Solution Methods. 7.4.3 Decoupled Power Flow. 7.5 Applications and Optimal Power Flow. 8. System Performance. 8.1 Reliability. 8.1.1 Measures of Reliability. 8.1.2 Valuation of Reliability. 8.2 Security. 8.3 Stability. 8.3.1 The Concept of Stability. 8.3.2 Steady-State Stability. 8.3.3 Dynamic Stability. 8.3.4 Voltage Stability. 8.4 Power Quality. 8.4.1 Voltage. 8.4.2 Frequency. 8.4.3 Waveform. 9. System Operation, Management, and New Technology. 9.1 Operation and Control on Different Time Scales. 9.1.1 The Scale of a Cycle. 9.1.2 The Scale of Real-Time Operation. 9.1.3 The Scale of Scheduling. 9.1.4 The Planning Scale. 9.2 New Technology. 9.2.1 Storage. 9.2.2 Distributed Generation. 9.2.3 Automation. 9.2.4 FACTS. 9.3 Human Factors. 9.3.1 Operators and Engineers. 9.3.2 Cognitive Representations of Power Systems. 9.3.3 Operational Criteria. 9.3.4 Implications for Technological Innovation. 9.4 Implications for Restructuring. Appendix: Symbols, Units, Abbreviations, and Acronyms. Index.

To achieve optimum performance a number of CMOS design choices, such as the choice of logic family, requires a general model of the fraction of logic transitions that arise from spurious transitions (glitches). This fraction can then be used to estimate the additional power dissipation due to spurious transitions. Analysis and simulation of a ripple-carry adder is used to derive a conservative model for static circuits. Across most applications, a good conservative estimate for the fraction is 30 to 40% of the total number of logic transitions.

This paper presents a design CAD tool for automated design of digital CMOS VLSI circuits. In order to fit the circuit performance into desired specifications, a multi-objective optimization approach based on genetic algorithms (GA) is proposed and the transistor sizes are calculated based on the analytical equations describing the behavior of the circuit. The optimization algorithm is developed in MATLAB and the performance of the designed circuit is verified using HSPICE simulations based on 0.18µm CMOS technology parameters. Different digital integrated circuits were successfully designed and verified using the proposed design tool. It is also shown in this paper that, the design results obtained from the proposed algorithm in MATLAB, have a very good agreement with the obtained circuit simulation results in HSPICE.

The authors present a new and fully hierarchical approach to automatic test-pattern generation, for digital MOS VLSI circuits. The description of a VLSI circuit consists of several hierarchical levels of interconnected modules. Each module consists of one or more sub-modules are functionally described by ordered binary decision diagrams (OBDD). The OBDDs of its sub-modules, starting from the lowest-level modules. Test-patterns are generated for each module using previously generated test-patterns for its sub-modules, starting at the switch-level. Accurate fault models, like the line stuck-at and switch stuck-on/open models, are used to model physical defects. At higher levels, faults are modeled by the test-patterns covering the fault. Results on large combinatorial circuits confirm the feasibility of the new test-pattern generation approach, and its superiority over conventional non-hierarchical methods. >

Capacitive coupling is the primary source of noise in nanometer technology digital CMOS VLSI circuits. It becomes worse with technology scaling. The interconnect capacitive crosstalk noise can be characterized by two parameters: peak noise voltage, and delay uncertainty. Delay uncertainty optimization can be seen as a subset of interconnect delay optimization. This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that cross-capacitances are optimally shared for simultaneous noise and delay minimization. Using an Elmore delay model including cross capacitances for a bundle of wires and well-known crosstalk models, we show that "symmetric hill" wire ordering according to the strength of signal drivers, which is known to optimize channel timing characteristics, can be used also for minimizing channel noise metrics. Examples using state-of-the-art circuits in 65-nanometer technology are analyzed and discussed.

High level synthesis has been recognized in both academic and industrial circles as the next major advance in commercial design tools for digital CMOS VLSI circuits. The potential advantages of high level synthesis, such as reduced design time, improved opportunities for design space exploration, and ease of verification of the implementation against an executable specification, have been stated frequently in recent years [1].

This paper presents an iterative method for the analysis of bipolar corona associated with the ionized field around high-voltage bipolar direct-current (HVDC) transmission-line conductors. A new finite-element technique (FET) is proposed to solve Poisson's equation where the constancy of the conductors surface field at the corona onset value is directly implemented in the finite-element formulation. Satisfying the current continuity condition and updating the space-charge density are based on the application of Kirchoff's current balance law at each node of the finite-element grid and take the ion diffusion into account. In order to investigate the effectiveness of the proposed method, a laboratory model was built. It has been found that the calculated V-I characteristics and the ground plane current density profiles agreed well with those measured experimentally. The simplicity in writing the computer program, in addition to the low number of iterations required to achieve convergence, characterize the new method of analysis.

This paper presents an iterative method for the analysis of bipolar corona associated with the ionized field around high-voltage bipolar direct-current (HVDC) transmission line conductors. A new finite element technique (FET) is proposed to solve Poisson's equation where the constancy of the conductors' surface field at the corona onset value is directly implemented in the finite element formulation. Satisfying the current continuity condition and updating the space charge density are based on the application of Kirchoff's current balance law at each node of the finite element grid and takes the ion diffusion into account. In order to investigate the effectiveness of the proposed method, a laboratory model was built. It has been found that the calculated V-I characteristics and the ground plane current density profiles agreed well with those measured experimentally. The simplicity in writing the computer program in addition to the low number of iterations required to achieve convergence characterize the new method of analysis.

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to "design-in" quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits.

Lately, research has been focused on the problem of extracting the main unsatisfiable cores from infeasible constraints. The main reasons of infeasibility can be represented by subsets of unsatisfied clauses referred to “Minimal Correction Subsets”. Various developed algorithms for computing MCSes can be used for fault detection technique which is considered a core of SAT-based Automatic Test Pattern Generation (ATPG) on digital VLSI circuits. This paper presents an efficient CPU-GPU algorithm for extracting the complete MCSes that can be optimized on NVIDIA General Purpose Graphics Processing Unit paradigm which is considered one of the most common platforms for GPU parallel computing. Our proposed algorithm is evaluated using a C++ algorithm for generating and reducing a SAT instance of VLSI digital circuits from ISCAS'85, ISCAS'89 and synthetic benchmarks. The proposed algorithm, utilizing our presented parallel SAT-solver, delivers about 1.4x speedup compared to the CUDA@SAT tool.

Analog Design Issues in Digital VLSI Circuits and Systems