Efficient VLSI Layout of WK-Recursive and WK-Pyramid Interconnection Networks

Supercomputers are today made up of hundreds of thousands of nodes. The interconnection network is responsible for connecting all these nodes to each other. Different interconnection networks have been proposed; high performance topologies have been introduced as a replacement for the conventional topologies of recent decades. A high order, a low degree and a small diameter are the usual properties aimed for by such topologies. However, this is not sufficient to lead to actual hardware implementations. Network scalability and topology simplicity are two critical parameters, and they are two of the reasons why modern supercomputers are often based on torus interconnection networks (e.g., Fujitsu K, IBM Sequoia). In this paper we first describe a new topology, torus-connected cycles (TCCs), realizing a combination of a torus and a ring, thus retaining interesting properties of torus networks in addition to those of hierarchical interconnection networks (HINs). Then, we formally establish the diameter of a TCC, and deduce a point-to-point routing algorithm. Next, we propose routing algorithms solving the Hamiltonian cycle problem, and, in a two dimensional TCC, the Hamiltonian path one. Correctness and complexities are formally proved. The proposed algorithms are time-optimal.

The increasing of the signaling technology motivated the research community to find alternative solutions to replace the sequential computing systems. These systems reached their limits, and it became an infeasible choice to manage the computational grand challenges. Thereby, many types of research have been conducted to improve a system with special characteristics able to cope with the new technology. Massively parallel computer (MPC) systems have been emerged to solve the complex computing challenges in parallel and concurrently. The performance of these systems is affected by the structure of the underlying interconnection network. Therefore, many designs of interconnection networks topologies have been presented looking for an optimal one. In this paper, we present the architecture of MMN which is a hierarchical interconnection network. The static and dynamic performance parameters of MMN have been evaluated in previous studies, and it provided good results compared to the conventional interconnection network topologies. This paper will focus on evaluating and determining the static cost-effective parameter of MMN which is the product of the relation between the node degree, network diameter, wiring complexity, and the total number of nodes in each network.

Effective Connectivity Reveals Largely Independent Parallel Networks of Face and Body Patches

This paper describes how new learning methods may make it possible for a large‐scale, hierarchical neural network to recognize most Japanese handwritten characters. This is a very large and complex task, as the Japanese character set consists of about 3000 categories which can be written in many different ways. Such a difficult task can lead a neural network to converge very slowly and to yield recognition rates that are uneven between categories. To address these problems we here propose five learning methods as modifications of the conventional back‐propagation learning rule. These methods produce fast convergence, even recognition rates over all categories, and adequate recognition of test samples. We also describe how a large‐scale neural network can be built by dividing the recognition task into several subtasks, with networks for each subtask, and then integrating these subnetworks in a large network with a hierarchical structure. In a hierarchical network, the upper level network directly integrates outputs from each lower level network. Application of that network to handwritten Japanese character recognition has resulted in poor recognition, because lower level networks do not know about unknown input patterns, and the direct integration of ambiguous outputs from many lower level networks confuses the upper level network. We propose a new integration method which provides each subnetwork with more information as to how close an input pattern is to the categories of that subnetwork. This method resulted in high recognition performance for character recognition. We here described the above methods, and report the performance of our implementation of a neural network for the recognition of 71 Hiragana characters, and describe our implementation of this network on a hypercube concurrent computer.

Scheduling multicasts on unit-capacity trees and meshes

In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high-degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two-dimensional mesh and torus topologies with shorter local links. This paper focuses on doubling the degree of common 2D meshes and tori while still preserving an attractive layout for VLSI design. By adding a set of diagonal links in one direction, diagonal networks are obtained. By adding a second set of links, networks of degree eight are built, named king networks . This research presents a comprehensive study of these networks which includes a topological analysis, the proposal of appropriate routing procedures and an empirical evaluation. King networks exhibit a number of attractive characteristics which translate to reduced execution times of parallel applications. For example, the execution times NPB suite are reduced up to a 30 percent. In addition, this work reveals other properties of king networks such as perfect partitioning that deserves further attention for its convenient exploitation in forthcoming high-performance parallel systems.

A performance analysis of a class of hierarchical interconnection networks is presented. The analysis includes both static analysis (i.e. queueing delays are neglected) and queueing analysis. In both cases, the hierarchical networks are shown to have better cost-benefit ratios. The queueing analysis is also validated by several simulation experiments. The impact of two performance enhancement schemes-replication of links and improved routing algorithms-on hierarchical interconnection network performance is also presented. >

Network cost and fixed-degree characteristic for the graph are important factors to evaluate interconnection networks. In this paper, we propose hierarchical Petersen network (HPN) that is constructed in recursive and hierarchical structure based on a Petersen graph as a basic module. The degree of HPN(n) is 5, and HPN(n) has \(10^n\) nodes and \(2.5 \times 10^n\) edges. And we analyze its basic topological properties, routing algorithm, diameter, spanning tree, broadcasting algorithm and embedding. From the analysis, we prove that the diameter and network cost of HPN(n) are \(3\log _{10}N-1\) and \(15 \log _{10}N-1\), respectively, and it contains a spanning tree with the degree of 4. In addition, we propose link-disjoint one-to-all broadcasting algorithm and show that HPN(n) can be embedded into FP\(_k\) with expansion 1, dilation 2k and congestion 4. For most of the fixed-degree networks proposed, network cost and diameter require \(O(\sqrt{N})\) and the degree of the graph requires O(N). However, HPN(n) requires O(1) for the degree and \(O(\log _{10}N)\) for both diameter and network cost. As a result, the suggested interconnection network in this paper is superior to current fixed-degree and hierarchical networks in terms of network cost, diameter and the degree of the graph.

OpenAirInterface is an experimental open-source real-time hardware and software platform for experimentation in wireless communications and signal processing. With the help of OpenAirInterface, researchers can demonstrate novel ideas quickly and verify them in a realistic environment. Its current implementation provides a full open-source software modem comprising physical and link layer functionalities for cellular and mesh network topologies. The physical (PHY) layer of the platform targets fourth generation wireless networks and thus uses orthogonal frequency division multiple access (OFDMA) together with multiple-input multiple-output (MIMO) techniques. The current hardware supports 5 MHz bandwidth and two transmit/receive antennas. The media access (MAC) layer of the platform supports an abundant two-way signaling for enabling collaboration, scheduling protocols, as well as traffic and channel measurements. In this paper, we focus on the mesh topology and show how to implement a single-frequency mesh network with OpenAirInterface. The key ingredients to enable such a network are a dual-stream MIMO receiver structure and a distributed network synchronization algorithm. We show how to implement these two algorithms in real-time on the OpenAirInterface platform. Further more, we provide results from field trials and compare them to the simulation results.

In this chapter we apply communication complexity to obtain methods for proving lower bounds on the complexity measures of VLSI circuits. A VLSI circuit is a more powerful computing model than the Boolean circuit model. While the gates (processors) of VLSI circuits are as simple as the gates of Boolean circuits, the communication structure (the graph describing the connections between processors) of VLSI circuits may contain cycles. This requires that a computation of a VLSI circuit be considered as an alternating sequence of synchronized steps C1, D1, C2, D2 ..., where Ci are communication steps and Di are working steps. In every communication step each directed edge (p 1, p 2) (communication link) transfers a binary value as the output of the processor pl to the processor p2. In every working step each node (processor) of the VLSI circuit computes outputs according to the values of its inputs. This contrasts to the Boolean circuits, where each processor and each directed edge were at most once active in the whole computation on an input. The main complexity measures of the VLSI circuit model are layout area A and time T (the number of working steps) . Since many computing problems may be solved with small area A if one allows a large time T and with small T if one allows relatively large A, one prefers to consider tradeoffs of complexity measures like A. T, A• T2 in order to objectify the measurement of the hardness of computing problems.

Communication performance comparisons, in terms of message latency, between mesh and hierarchical ring interconnection networks for shared-memory multiprocessors are developed. Traffic in the networks is assumed to consist of the short, fixed-length messages needed for remote-memory read/write operations and cache coherency control. Square-mesh networks with bidirectional links and no end-around connections are compared to two- and three-level hierarchical rings. Wormhole routing is used in the meshes, with messages consisting of / flits, with each flit containing b bits. In the ring networks, each ring segment can contain a complete message of f × b bits. Meshes and three-level rings provide comparable delays for system sizes of up to 200 or 300 processor clusters. The delay comparisons are valid only for the lightly loaded traffic case in which contention and blocking are low. This is the situation in practical shared-memory multiprocessor systems with a low cache miss rate and a high physical locality of reference in the global address space.

The Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing The system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling, and development. System software includes a translator for the INSIGHT language, a parallel debugger, low and high level simulators, and a message passing system for all control needs. Image processing application software includes a variety of point operators neighborhood, operators, convolution, and the mathematical morphology operations of binary and gray scale dilation, erosion, opening, and closing.

In this paper, we explore the use of a pseudo-random graph family, Borel Cayley graph family, as the network topology in an NGN (Next Generation Network) with thousands of nodes operated in a packet switching environment asynchronously. BCGs are known to be an efficient topology in interconnection networks because of its small diameters, short average path lengths, and low-degree connections. However, the application of BCGs in NGN are hindered by a lack of size flexibility and fault tolerant routing. We propose a fault-tolerant routing algorithm for BCGs. Our algorithm exploits the vertex-transitivity property of Borel Cayley graphs and relies on extra information to reflect topology change. Our results show that the proposed method supports good reachability and short average hop count.

The perfect hierarchical hypercube (HHC) interconnection network has been introduced in the literature recently. Due to its hierarchical structure, an HHC can connect a significant number of nodes while retaining a low degree and a small diameter. In this paper we describe an algorithm solving the set-to-set disjoint-path routing problem in perfect hierarchical hypercubes. In an HHC2m+m, given two sets S and D both containing k (≤ m + 1) nodes, the proposed algorithm finds k node-disjoint paths between the nodes of S and the nodes of D of lengths at most (m+1)(2m+k+1)+3 in O(km2m) time complexity.

Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present NoC architecture based on Mesh-of-Tree (MoT) deterministic routing. MoT interconnection has the advantage of having small diameter as well as large bisection width. It is known as the fastest network when considered solely in terms of speed. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented by using FIFO in mixed clock system.