Comprehensive Study of Various Short Failures on Printed Circuited Board

A printed circuit board (PCB) is an essential element for practical circuit applications and its failure can inflict large financial costs and even safety concerns, especially if the PCB failure occurs prematurely and unexpectedly. Understanding the failure modes and even the failure mechanisms of a PCB failure are not sufficient to ensure the same failure will not occur again in subsequent operations with different batches of PCBs. The identification of the root cause is crucial to prevent the reoccurrence of the same failure. In this work, a step-by-step approach from customer returned and inventory reproduced boards to the root cause identification is described for an actual industry case where the failure is a PCB burn-out. The failure mechanism is found to be a conductive anodic filament (CAF) even though the PCB is CAF-resistant. The root cause is due to PCB de-penalization. A reliability verification to assure the effectiveness of the corrective action according to the identified root cause is shown to complete the case study. This work shows that a CAF-resistant PCB does not necessarily guarantee no CAF and PCB processes can render its CAF resistance ineffective.

Purpose – This paper aims to describe the development of an approach that uses a flexible substrate to investigate the mechanism of conductive anodic filament (CAF) growth and effect of different material and manufacturing variables. Design/methodology/approach – A new approach using a simulated test vehicle (STV) has been developed to study the CAF phenomena. The STV can be easily built under controlled conditions in the laboratory using different glass fibres and resin powder to investigate the effect of different variables separately on CAF. The advantage of the STV is that CAF can be formed in relatively short period in a controlled way, and CAF growth can be easily identified using a back-lighting under a microscope due to the thin flex material used as the test sample. Findings – STV has been used to investigate a number of effects on CAF formation: different glass fibres, reflow process, acid contamination in drilled holes, desmear process and glass bundle size. The results demonstrate that for finished fibres acid contamination (plating solution) at the electrode was necessary for CAF formation. However, for unfinished glass fibres (loom state and heat cleaned) CAF can be formed without acid contamination. The reflow process significantly increases CAF formation. Running an aggressive desmear process and using large glass fibre bundle also increased CAF formation. Originality/value – This new approach will be of benefit for printed circuit board (PCB) supplier to evaluate CAF performance on different resin systems and glass fibres to provide high CAF resistance quality PCBs. The test period (168 hours) would be much shorter than the traditional CAF testing (1,000 hours).

A thin Sn coating was coated on the Cu electrodes on a printed circuit board (PCB) and annealed to form Cu/Sn intermetallic compounds (IMCs). Electrochemical migration (ECM) characteristics were investigated with respect to coating thickness, conductor spacing, and potential bias. From the anodic polarization test, the corrosion current of Cu/Sn IMCs was reduced to nearly two orders of magnitude at 0.217 V (versus saturated calomel electrode) compared to pristine Cu. The corrosion resistance of Cu/Sn IMCs was improved. Water drop test (WDT) results revealed that mean time to failure also increased over 50 times on the sample with the Sn coating (160 nm) at 50- μm spacing compared to the pristine Cu and a thick Sn coating (160 nm) was more effective than thin Sn coating (90 nm) due to the formation rate of IMCs. Passivity behavior and pitting corrosion were observed in both the anodic polarization test and the WDT. The graph of current-density potential in the anodic polarization test and the TTF potential in the WDT showed a quite similar curve shape. Therefore, dissolution step is the rate-determining step in ECM and governs the entire ECM process. Cu/Sn IMCs can be a new alternative surface barrier to improve the ECM resistance of Cu electrodes on PCBs.

The drive toward more compact, highly functional, and portable electronic devices has forced a reduction in conductor spacing. According to the 2006/2007 IPC Technology Roadmap, today’s drilled holes are a minimum of 0.20 mm in diameter with via pitch at 0.60 mm. State-of-the-art is 0.15 mm with 0.40 mm via pitch and future trends in the near future reduce these to 0.10 mm holes and 0.35 mm vias. A direct reliability concern with reduced pitch designs is an electrochemical failure mode in printed wiring boards (PWBs) known as conductive anodic filament (CAF) formation. CAF—a copper-containing salt which grows subsurface from the anode to the cathode has been identified as Cu2(OH)3Cl. When the CAF bridges between the two holes, catastrophic failure can occur because this salt has semiconductor properties. CAF growth is enhanced by higher voltage gradient and closer spacing. CAF test coupon designs must take into account a number of factors in the board manufacturing process which will affect the reproducibility of the coupons. These include glass fiber style, resin type, and content, as well as the drilling parameters such as drill bit wear, speed, diameter, and drilling sequence. The closer spacing identified in the IPC Roadmap creates hole-edge to hole-edge conductors that can be problematic. Cracking between barrels can occur during the drilling process, especially for more brittle laminate materials. During the plating process, residues can accumulate in the cracks. Subsequent testing under humidity and bias conditions will lead to shorts which can be mistaken for CAF. This paper will identify the limitations in designing a PWB for CAF reliability testing.

With the miniaturization of the electronic devices, the spacing among the circuit traces on printed circuit boards (PCB) keeps reducing, which increases the risk of insulation failure based on electrochemical migration (ECM), especially for immersion silver (ImAg) plated PCB. Meanwhile, due to the severe air pollution in developing countries, airborne dust can deposit on the PCBs in electronic devices. The soluble salts in the dust can decrease critical humidity and increase the ion concentration in the moisture condensed on the PCB surfaces, so that the failure mechanism based on ECM may be changed and the time to failure (TTF) can be shorten. In this paper, the effect of the soluble salt with various concentrations on the ECM failure on PCB was investigated. The life model of ECM was built up based on the electrochemical reactions on electrodes. Then the ECM of PCB under sodium chloride (NaCl) solution with various concentrations was simulated on Y- pattern PCB by water drop (WD) test method. The failure characteristics of ECM during various stages of migration and under various concentrations of salt solution were analyzed by the morphology and element compositions of dendrite products, as well as real time monitoring of surface insulation resistance (SIR). The TTF of ECM was extracted to fit the life model. Finally, the mechanism and performance of ECM of PCB under salt solution was analyzed. And the application of the life model of the ECM failure of PCB contaminated by soluble salts was discussed.

With lead-free legislation impacting printed circuit board (PCB) manufacturing, immersion silver (ImAg) finish is adapted as the top finish of copper trace on PCB due to its many advantages. However, it is easy for silver to form electrochemical migration (ECM) in high humid environment, so that the potential bias and spacing between adjacent circuits are limited. In addition, since the thickness of ImAg finish is usually less than 0.15µm restrained by the electroless plating process, the copper trace under the silver finish cannot be fully covered, which causes the complexity of corrosion and electrochemical migration. In this paper, water drop test was used to induce the electrochemical migration on ImAg finished “Y” pattern circuits on PCB. The surface insulation resistance was detected by a picoammeter and the growth of dendrite deposit between two electrodes was monitored by a video system. The electrolytic reaction and galvanic reaction on the electrodes formed by bimetal couples was analyzed theoretically. The mechanism of electrochemical migration of copper driven by immersion silver finish was discussed. The effects of potential bias, spacing and electric field intensity between adjacent circuits on electrochemical migration were discussed.

The effect of epoxy/glass interfaces on CAF failures in printed circuit boards

Electrochemical migration (ECM) of solder joining can result in the growth of a metal deposit with dendrite structure from cathode to anode. In electronic device, this phenomenon potentially leads to the incompetence or failure of whole devices. In this paper, the ECM behaviour of printed circuit boards (PCBs) with SAC 0307, one of the low-cost lead-free solder alloys with less silver content, has been studied. The corrosion behaviour of SAC 0307 has been investigated by using sodium chloride solution in different concentrations which is between 0.01 M to 1.0 M as a medium. A Water Drop Test (WDT) was carried out and the time-to-failure of each sample has been recorded. After WDT test, the dendrite phase was identified using Variable Pressure Scanning Electron Microscope (VPSEM) with Energy Dispersive X-ray Spectroscopy (EDX) and X-ray Photoelectron Spectroscopy (XPS) to investigate its surface morphology and corrosion products. As results, it has been found that the corrosion susceptibility of SAC 0307 is greatly influenced by the concentration of the medium solution used. The voltage drop occurred was due to the dendrite grew at the cathode electrode on the PCBs and expanded to the anode electrode, indicating a significant effect of aggressive behaviour of the medium used. The rate of the dendrite growth was affected by the concentration of the medium used. The main element found in the dendrites on the SAC 0307 on PCBs was Tin as it is more mobile than Cu.

One of the main challenges in the electronics manufacturing and packaging development is how to integrate more functions inside the same or even smaller size. To meet the demand for higher integration, the interest toward passive and active component embedding has been increasing during the past few years. One of the main reasons for the growing interest toward embedded active components, in addition to demand for higher packaging density, is the need for better electrical performance of the component assemblies. However, it is little known how embedded IC and passives affect the reliability of IC packaging. Solder joints have been used in the electronic industry as both structural and electrical interconnections between electronic packages and printed circuit boards (PCB). When solder joints are under thermal cyclic loading, mismatch in coefficients of thermal expansion (CTE) between the printed circuit boards and the solder balls creates thermal strains and stresses on the joints, which may finally result in cracking. Consequently, the mechanical interconnection is lost, leading to electrical failures (such as hard/intermittent open, parametric failure), which in turn causes malfunction of the circuit or whole system. When a die is embedded into a substrate, Young's modulus of the die is larger than one of the core of the substrate and the CTEs of the die is smaller than those of the substrate. As a result, mismatch in coefficients of thermal expansions (CTE) between the substrate with the embedded device and the solder balls may increase. In the present study, the stress of chip scale packages (CSP) with an embedded die under thermal cycling conditions is evaluated using the finite element method. The viscoplastic model for solders including matrix dislocation mechanism and grain boundary sliding model developed by Yi et al. (2002) is employed.

This paper discusses the thermal management challenges presented when using power flip chips on organic laminate structures, and evaluates design variables that would produce the lowest thermal resistance between the die surface and a product housing. Power integrated circuits are often mounted in a package that features design elements for both electrical interconnect and thermal management. One such package is the TO-220. This package allows the electrical interconnect path to be separate from the thermal path by using the center pin as the electrical connection for the drain, and the tab as the thermal management path. When this package is not used, and the die is placed directly on the Printed Circuit Board (PCB) as a flip chip, the electrical and thermal paths come very close in proximity, creating conflicting requirements under the flip chip. This paper addresses these issues and proposes a solution for thermally managing a power flip chip. Included in this paper are basic design options for optimizing the thermal path and how it interacts with electrical interconnect requirements. Specific chip design considerations such as flip chips with two sets of solder bumps for thermal and electrical connection are discussed. Unique PCB technologies including embedded heat-sinks are also evaluated. Detailed evaluations using Finite Element Analysis (FEA) models are shown to determine the optimized design and the interaction between several variables including solder bumps, PCB vias and PCB thickness are discussed. Empirical test results using special thermal test die and various PCB configurations are also presented.

The use of Printed Circuit Board (PCB) technology for device packaging offers new opportunities to solve these challenges. During the past decade embedding of semiconductor chips into PCB structures evolved from a research topic to volume production. The paper will briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia and Europe, mainly for mobile applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to reduce the thickness and size of the module. In order to replace DCB ceramics, a structure of thermal laminate material between Cu layers has been developed and the capability for thermal conduction and electrical insulation has been evaluated. For the assembly of large power IGBTs with sizes of 100 mm² and larger, new silver sintering pastes have been evaluated. They enable a pressure-less sintering at 200 °C, compatible with PCB materials. To handle the high switching current of up to 200 A, suitable copper tracks in the PCB are required. The realization of such thick copper lines with thickness up to 1 mm requires advanced processing, compared to conventional multilayer PCB production. In order to form complex power systems out of modules with embedded chips interconnections by Ag sintering are under development.

Advanced electronic packaging materials play a key role in the proper functioning and useful life of the packaged electronic assembly. These functions mainly include electrical conduction, electrical insulation, mechanical support and structural profiles, environmental protection, as well as thermal conduction and dissipation. Therefore, electronic packaging materials shall possess required electrical, mechanical, thermal, chemical, and physical properties to provide the electronic system with excellent performance and reliable functions. For example, metals provide the means for conducting signals throughout the system via thin-film conductors, wires, interconnects, vias, etc.; insulating materials are used to prevent loss of signal currents by confining them to the metal path; structural or multifunctional materials are used to provide physical functions and mechanical support; and there are materials in which the primary function is for thermal dissipation or to prevent the system from the environment. This chapter will provide an overall review for the state of the art of high-performance electronic packaging materials and their thermal management functions, including properties of key materials, state of maturity, applications, processing, and future directions. These materials mainly include metallic materials, ceramics and semiconductors, electronic glasses, polymers, multimaterial laminates, printed circuit board (PCB) materials, thermal interconnection materials, low thermal conductivity materials, and advanced thermally conductive materials.

The work in this paper is mainly on the grouping of printed circuit boards (PCBs) for Surface Mount Assembly in the electronics industry. The arrangement of PCBs among several surface mount machine lines is a typical kind of group technology (GT) problem. From literature, there are various clustering techniques developed to solve the clustering problems. In this paper, fuzzy c-means clustering (FCM) is used to solve the PCB grouping problem. The FCM is applied in a real problem and the result shows that there should be a systematic method to arrange the scheduling of PCB assemblies in electronic industry to improve the operations planning process.

Electrochemical migration and dendrite growth between two electrodes: Experiments and Brownian dynamics simulations

Silver-plated electronic devices are extensively used in microwave circuits. The electrochemical migration of silver in these circuit boards can affect high-frequency characteristics and signal integrity. In this work, the effect of silver migration on signal transmission of printed circuit boards was evaluated using both experimental testing and analytic modeling. The S parameters of circuit boards with silver migration were measured. Based on multi-conductor transmission line theory and electrical properties of dendrite-like electrochemical migrated silver, a distributed parameter circuit model for the circuit board with silver migration was developed. The model results are in good agreement with those obtained from the experimental tests. The results of this investigation provide a better understanding of the high-frequency behavior of a circuit board with silver migration and theoretical support for identifying failure features in fault diagnosis.