Computer aided routing for complex programmable logic device manufacturing test development

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.

Presents a complex programmable logic device (CPLD) based system for cracking the RC4 (Rivest Cipher 4) encryption algorithm. The system achieves an outstanding price/performance ratio, easily beating other low-cost approaches, such as commodity PCs. The system was implemented using a single Altera EPF10K20 CPLD on an Altera UP1 Education Board. This CPLD is large enough to contain the control unit and five functional units. Measured performance on our prototype shows that we can crack a 32-bit RC4 in an expected time of 15 hours (30 hours worst case). This gives a theoretical expected time of 159 days to crack 40-bit keys-the maximum possible key length that can exported from Canada and the USA. Our results demonstrate the effectiveness of programmable logic (CPLD or FPGA) against even a cryptosystem designed for software implementation.

The paper focuses on the methodology of designing a cyber physical systems (CPS) physical layer using programmable devices. The CPS physical layer can be implemented in programmable devices, which leads to a reduction in their costs and increases their versatility. One of the groups of programmable devices are complex programmable logic devices (CPLDs), which are great for energy-saving, low-cost implementations but requiring flexibility. It becomes necessary to develop mathematical CPS design methods focused on CPLD. This paper presents an original technology mapping method for digital circuits in programmable array logic (PAL)-based CPLDs. The idea is associated with the process of multilevel optimization of circuits dedicated to minimization of the area of a final solution. In the technology mapping process, the method of a multioutput function was used in the graph of outputs form. This method is well known from previous papers and proposes optimization of a basic form of the graph of outputs to enable better use of the resources of a programmable structure. The possibilities for the graph of outputs were expanded in the form of sequential circuits. This work presents a new form of a graph that describes the process of mapping and is known as the graph of excitations and outputs. This graph enables effective technology mapping of sequential circuits. The paper presents a series of experiments that prove the efficiency of the proposed methods for technology mapping. Experiments were conducted for various sizes of PAL-based logic blocks and commercially available CPLDs. The presented results indicate the possibility of more effective implementation of the CPS physical layer.

In order to improve the traditional speed-tension type three-motor synchronous control platform based on PLC bus control to further enhance the speed and control accuracy of the control system, enhance the control effect, Speed-Tension type Three-motor coordinate synchronous control platform based on Multi-microprocessor is proposed in this paper.In this platform, the complex programmable logic devices (CPLD), Digital Signal Processor (DSP) and microcontroller (MCU) are combined.In order to improve rapid and synchronization of the control system, CPLD Parallel nature is used to achieve three serial ports synchronous and concurrency control; Complex control algorithms are implement by the use of DSP fast and efficient data processing capabilities; Experimental results show: The control system is stable, at the same baud rate the control speed of the platform based on multi-microprocessor is more than three times faster than the one of the traditional PLC bus control platform.In the multi-microprocessor control platform， under the same control algorithm regulation time is more fast 0.53 seconds than traditional PLC control platform, the overshoot of the system is 13.53% of the one using traditional PLC control platform, and the tracking the maximum error reduces 60.53% than the one of the traditional PLC control platform.

Digital Systems Design with FPGAs and CPLDs

In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.

The objective is to design and fabricate a wire programmable discrete version of an analog computer known as the digital differential analyzer (DDA) using the binary rate multiplier (BRM) principle without using analog components like operational amplifiers. The bandwidth of the elements can be more than 50kHz. The BRM enables arithmetic-free signal processing. Programming a DDA based on the BRM principle is very similar to the programming of an analog computer due to the structural similarity. The DDA described in this paper uses two wires each at the input and the output ports. One wire is used for carrying the magnitude of the signal in the pulse-rate form and the other wire for the sign of the signal. The paper aims at simulating and synthesizing various modules of a stand-alone-DDA and downloading the synthesized modules on to complex programmable logic devices (CPLDs). Interconnecting various modules in the CPLD can solve differential equations. The results obtained in real time were verified by simulation using (i) ModelSim, (ii) Simulink and (iii) analytical solution of equivalent Z-domain blocks.

Complex Programmable Logic Device (CPLD), the simplest hardware for implementing reconfigurable logic, and Micro controller have their specific advantages when implemented in their own domains. Most of the modern electronics circuits are implemented either only on CPLD or on Micro controller. If studied carefully, there are ways to implement both CPLD and controller on a single control circuit and use the advantages of both to the maximum. The field of Co-Design is about 10 years old[1]. The paper elaborates the implementation of such a design.

In this article, we introduce a set of online power quality monitor who is based on DSP (Digital Signal Processor). The monitor makes full use of DSP chip's strong operation capability. It can monitor power quality online, display real-time measure data and save super scalar data, which can provide accurate data to power quality evaluation and improvement. On the hardware side, the system takes DSP and CPLD as core of power parameter detection circuit, and complex programmable logic device (CPLD) and phase-locked loop (PLL) as synchronous sampling circuit, TO the software, designed relative software arithmetic. At the same time, the main program of electric power parameter detection was introduced. Experiments show the proposed system is of fast response, high accuracy, and real-time processing.

According to some casual observers, computer-aided design (CAD) tools are very similar. These tools are used to design new artifacts in a digital environment; hence, they share typical software components, such as a computing engine and human–machine interface. However, CAD software is dedicated to specific professionals – such as engineers, three-dimensional (3D) artists, and industrial designers (IDs) – who claim that, despite their apparent similarities, CAD tools are so different that they are not substitutable. Moreover, CAD tools do not fully meet the needs of IDs. This paper aims at better characterizing CAD tools by taking into account their underlying design logic, which involves relying on recent advances in design theory. We show that engineering CAD tools are actually modeling tools that design a generic variety of products; 3D artist CAD tools not only design but immediately produce single digital artifacts; and ID CAD tools are neither a mix nor an hybridization of engineering CAD and 3D artist CAD tools but have their own logic, namely to create new conceptual models for a large variety of products, that is, the creation of a unique original style that leads to a generic singularity. Such tools are useful for many creative designers beyond IDs.

The frame transfer Area Array Sensor with vertical antiblooming structure requires that all performance characteristics such as large charge capacity, high charge transfer efficiency, low read noise and low antiblooming voltage be optimized in a singlemanufacturable CCD (charge-coupled device). There is a common tendency to optimize one performance characteristic at the expense of others. With the goal of optimizing above all performance characteristics, a frame transfer area array sensors with vertical antiblooming structure is optimization designed by the CAD (computer aided design) tools and fabricated, which equal to twenty-six micron square pixel size with 516 (H) x1028 (V) active pixels(the channel stop is 4μm and the photosensitive area is 22x22 μmxμm). At first, it is simply introduced the modeling of the frame transfer area array sensors with vertical antiblooming structure from the top to down and simulated by the CAD tools combined with the process and device models. The essential design and calculation of the CCD with antiblooming function are discussed in detail. And the process, layout and device parameters to design this frame transfer area array sensors (including the impurity concentration and layer thickness of the P-well and the buriedchannel, and the design output amplifier) are optimized according to the above simulation. At the last, the device is fabricated and the performance characteristics ( e.g. charge capacity, charge transfer efficiency, read noise and antiblooming voltage) are test to compare the simulation. To demonstrate the process used to optimize this frame transfer area array sensors with vertical antiblooming structure, this paper contains test data for this kind of CCD device which is optimization designed and fabricated by the CAD (computer aided design) tools. The test datas shows the way using the CAD tools optimization design a frame transfer area array sensors with vertical antiblooming structure correct.

During the development of an electronic module using a complex programmable logic device (CPLD) and a micro-controller, we noticed an abnormal behavior of the CPLD manifested as an unexpected reset of a counter. We identified a synchronous perturbation and an asynchronous perturbation as being responsible for the disturbance, both of them being related to the change in the state of a large number of data lines. We devised and tested methods for eliminating both perturbations, the application of which helped in achieving the intended behavior of the device.

Programmable logic offers an alternative solution for the computationally-intensive functions found in digital signal processing (DSP). Programmable logic can provide increased DSP system performance at reduced system cost. Programmable logic combines the flexibility of a general purpose DSP plus the speed, density, and low cost of an ASIC implementation. In some applications, programmable logic replaces the DSP processor entirely. In others, programmable logic works in conjunction with the DSP processor, offloading the computationally-intensive function and freeing the processor for other functions. This paper describes an alternative to traditional, general-purpose DSP processors. Programmable logic can implement functions beyond the capabilities of today's DSP processors. Field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs) potentially provide performance increases of an order of magnitude over traditional DSPs with the same flexibility.

This article takes the helium optically pumped magnetometer which is widely used in mineral exploration and space magnetic field measurement as research object. It describes the principle of magnetic sensor and the basic structure of automatic tracking circuit. The research focuses on the modules of signal processing, frequency measurement and data processing in the optically pumped magnetometer. The measurement system which has the function of real-time data collection and display is designed based on CPLD (Complex Programmable Logic Device) and embedded system.