Routing algorithms for programmable logic device design and manufacturing test development

We describe a computer aided design (CAD) tool developed to facilitate manufacturing test development for complex programmable logic devices (CPLDs). The CAD tool specifically supports manual and semi-automatic routing for the Cypress Delta 39 K series CPLD for the purpose of manufacturing testing of the programmable interconnect network within the device as well as all programmable logic functions. Two routing algorithms were developed and proved to work correctly with the best one chosen based on complexity analysis. The resultant router CAD tool supports all CPLDs in the Delta 39 K series family and produces the configuration bits necessary to program or configure the CPLD for the extensive tests that must be applied to ensure that the manufactured CPLDs are defect-free. The router has also been used extensively in the verification portion of the design process of the Delta 39 K series CPLDs. While the router is specific to a particular CPLD, the basic approach, including features and algorithms, is applicable to any CPLD or FPGA where programmable routing resources must be specified to accurately test the device and provide design verification.

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.

Digital Systems Design with FPGAs and CPLDs

In this paper, the design and development of a pulse-frequency modulation (PFM) signal generator circuit toolbox targeting the programmable logic device (PLD) is presented. PFM is signal encoding scheme that realizes an analog signal level as a digital bit-stream where the bit-stream frequency is proportional to the analog signal level. It is analogous to pulsewidth modulation (PWM). A Python script is run which sets-up a project and the analog signal to encode into PFM. The user can then generate a PFM signal generator circuit description in VHDL for implementation within a field programmable gate array (FPGA) or complex programmable logic device (CPLD). In this paper, the Xilinx Cool runner-II CPLD is chosen as the target device into which the VHDL circuit description can be synthesized and configured into the CPLD. In addition, a MATLAB script is generated to allow for analysis in MATLAB and a SPICE netlist is generated for analog circuit simulation.

Digital design classes are increasingly using programmable logic devices (PLD) to augment the educational experience. Previous works discuss the advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), in digital logic design education and highlight the instructorpsilas experience of integrating these teaching methods in the classroom. This paper instead focuses on the studentspsila experience to determine the overall effectiveness of using PLD boards. By using statistics from a comprehensive survey that targets student feedback and opinion, and by comparing our classpsilas final exam scores with a previous class that did not use PLDs, we are able to informatively assess the benefits of using PLDs for digital design education.

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

Programmable logics, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs), are widely used in security applications. In these applications cryptographic ciphers, physically unclonable functions (PUFs) and other security primitives are implemented on such platforms. These security primitives can be the target of fault injection attacks. One of the most powerful examples of fault injection techniques is laser fault injection (LFI), which can induce permanent or transient faults into the configuration memories of programmable logic. However, localization of fault sensitive locations on the chip requires reverse-engineering of the utilized building blocks, and therefore, is a tedious task. In this work, we propose an automated technique using readily available IC debug tools to map and profile the fault sensitive locations of programmable logic devices in a short period.

According to some casual observers, computer-aided design (CAD) tools are very similar. These tools are used to design new artifacts in a digital environment; hence, they share typical software components, such as a computing engine and human–machine interface. However, CAD software is dedicated to specific professionals – such as engineers, three-dimensional (3D) artists, and industrial designers (IDs) – who claim that, despite their apparent similarities, CAD tools are so different that they are not substitutable. Moreover, CAD tools do not fully meet the needs of IDs. This paper aims at better characterizing CAD tools by taking into account their underlying design logic, which involves relying on recent advances in design theory. We show that engineering CAD tools are actually modeling tools that design a generic variety of products; 3D artist CAD tools not only design but immediately produce single digital artifacts; and ID CAD tools are neither a mix nor an hybridization of engineering CAD and 3D artist CAD tools but have their own logic, namely to create new conceptual models for a large variety of products, that is, the creation of a unique original style that leads to a generic singularity. Such tools are useful for many creative designers beyond IDs.

The frame transfer Area Array Sensor with vertical antiblooming structure requires that all performance characteristics such as large charge capacity, high charge transfer efficiency, low read noise and low antiblooming voltage be optimized in a singlemanufacturable CCD (charge-coupled device). There is a common tendency to optimize one performance characteristic at the expense of others. With the goal of optimizing above all performance characteristics, a frame transfer area array sensors with vertical antiblooming structure is optimization designed by the CAD (computer aided design) tools and fabricated, which equal to twenty-six micron square pixel size with 516 (H) x1028 (V) active pixels(the channel stop is 4μm and the photosensitive area is 22x22 μmxμm). At first, it is simply introduced the modeling of the frame transfer area array sensors with vertical antiblooming structure from the top to down and simulated by the CAD tools combined with the process and device models. The essential design and calculation of the CCD with antiblooming function are discussed in detail. And the process, layout and device parameters to design this frame transfer area array sensors (including the impurity concentration and layer thickness of the P-well and the buriedchannel, and the design output amplifier) are optimized according to the above simulation. At the last, the device is fabricated and the performance characteristics ( e.g. charge capacity, charge transfer efficiency, read noise and antiblooming voltage) are test to compare the simulation. To demonstrate the process used to optimize this frame transfer area array sensors with vertical antiblooming structure, this paper contains test data for this kind of CCD device which is optimization designed and fabricated by the CAD (computer aided design) tools. The test datas shows the way using the CAD tools optimization design a frame transfer area array sensors with vertical antiblooming structure correct.

A collision avoidance system, also known as a pre-crash system, forward collision warning system, or collision mitigation system, is a sophisticated driver-assistance system that aims to avoid or mitigate the severity of a collision. For this research, collision avoidance system will be fabricating to show that this system can detect avoidance range before apply the braking action to prevent collision. The ultrasonic sensor will be used in this system to detect the avoidance range. In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). This research will observe how to implement FPGA and CPLD in the collision avoidance system using VHSIC Hardware Description Language (VHDL). The VHDL will be done in Quartus II 15.0 Software. In this research, Terasic DE-10 Standard board has been used. It contains FPGA microcontroller model Cyclone V SoC 5CSXFC6D6F31C6N. Max II board is used because it contains CPLD microcontroller model EPM240T100C5.

A reconfigurable interconnection network (RIN) is a custom-designed on-chip switching network yielding routing solutions for a pre-given set of applications. Like field programmable gate array (FPGA) routing networks, the RIN is used to make reconfigurable interconnections among functional blocks. Unlike FPGAs, the network topology of a RIN is irregular as it is designed for a given set of routing requirements and optimized for the area cost subject to given delay constraints. In this paper, we propose an automatic design scheme for RINs, including routing specification formulation, graph modelings, network topology designs, routing algorithms and multiplexer-based network circuit implementation. The choice of the design scheme is based on the existing routing network design practices and research, which give feasible solutions. Our scheme is to optimize the designs with the choice of design parameters. A computer-aided design (CAD) tool is developed based on the design scheme, which takes a set of routing requirements as input and produces the corresponding RIN network topology and network circuit in hardware description language format. We present the area costs of various RINs generated by the CAD tool subject to delay constraints, and illustrate the RIN design scheme with a reconfigurable multistream video system.

Additive manufacturing has opened the door to the creation of lightweight lattice structures. However, present Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) software are unsuitable for these types of structures. The objective of this research is to examine the performances of current CAD and CAE software to design lattice structures and to demonstrate their limitations and propose requirements for future developments. A performance evaluation of a case study for lattice structure designs was conducted. The criteria used for the evaluation were CAD human-machine-interface, RAM consumption, data exchange between CAD, CAE and CAM tools and finite element analysis (FEA) duration and file sizes. The CAD tool was incapable of executing a repetition function for octet-truss lattice structures of 150 x 150 x 150 mm dimensions or larger and the software stopped working. For 70 × 70 × 70 mm octet-truss lattice structure, the FEA computation file size reached 36.6 GB. The CAD file size of a 200 x 200 x 200 mm octet-truss lattice structure reached nearly 290 MB. In conclusion, this study exposes the performance inadequacy of current CAD and CAE tools and CAD file formats to design lattice structures for additive manufacturing parts.

Chapter 10 - Programmable Logic Devices

Computer-aided design (CAD) software for programmable logic devices (PLDs) provides the link between design for programmable logic and the fuse pattems required to program the devices. This article reports an investigation into the current state of CAD support for PLDs. The study was necessary background to defining the requirements of a logic synthesis system for PLDs. Aspects of PLD CAD systems of particular relevance are the specification languages and capabilities of the packages. These directly relate to components of the synthesis system and its output format. The article attempts to provide recommendations and conclusions with regard to this.

Following the vision of Industry 4.0, manufacturers started to break down products into subsystems, each of which is developed and supplied by different suppliers to tackle the increasing complexity of product development (e.g., in vehicle, machine or plant construction). This process needs to be supported by intuitive Computer-Aided Design (CAD) tools and virtual modeling and simulation environments to effectively meet the challenges of increasingly complex product development. Therefore, in this paper, we present some outcoming of a research project called DisMoSim ( Dis tributed Mo deling and Sim ulation), which proposes an intuitive virtual environment for modeling and simulation that embeds a Multi User Inverse Kinematic Solver (MUKS). The MUKS allows (i) individual subsystems to be tested intuitively, i.e., Rapid Testing (RT), and (ii) people not yet familiar with a subsystem to understand it easily and quickly through simple kinematic actions, i.e., Rapid Understanding (RU), without unnaturally interrupting the modeling process. Finally, (iii) the MUKS enables subsystems to be easily assembled into complete systems, i.e., Rapid Assembling (RA), by means of a so-called snapping-point mechanism which supports the complex process of aligning and assembling different subsystems. To evaluate these capabilities, we present the results of a user study conducted with 20 participants. Special attention has been given to the embedded MUKS in contrast to existing approaches known from common CAD and simulation software. Thus, we demonstrate the practicability, usability, and versatility of our approach. • Finding modeling and simulation errors in CAD models is cumbersome with current tools. • CAD tools need intuitive means for testing during modeling. • Inverse kinematic solvers allow for rapid prototyping and testing in CAD systems. • New user interface and interaction paradigms ease interaction with CAD tools.