Report on existing CAD support for programmable devices

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

Since the emergence of Computer Aided Design (CAD) software in 1957, educators have been committed to equipping design engineering students with proficiency in the most widely employed CAD tools in the industry. In the early days, training focused on step by step instructions and understanding CAD theory. Overtime, lecturers adopted more hands-on practice, project-based learning and collaborative learning techniques [1]. The abundance of online resources and tutorials has allowed lecturers, particularly in Higher Education (HE), to focus less on training and more on theory and use of various software and techniques. Over the last decade, the number, pace and emergence of unique sub-sector software development has grown exponentially, making it difficult for educators to adopt a fixed CAD curriculum. In the early days, the dominant players in the CAD software arena until the early 2010s were Solidworks, Rhino 3D, and Autodesk Maya, each equipped with its own proprietary rendering engine. However, over the past decade, there has been a proliferation of CAD software alternatives, complemented by independent rendering engines like Keyshot, notably embraced by software applications such as Blender, Gravity sketch, and Sketchup. In particular, Blender and Rhino's Grasshopper add-on have experienced a surge in user-generated custom add-ons, broadening the array of available features and functionalities. The rapid expansion of Artificial Intelligence (AI) tools over the last two years has introduced a new layer of complexity, as tools such as Midjourney, Stable Diffusion, and Control Net have gained prominence in the industry. The exponential growth of computational tools available has presented higher education institutions with a perplexing choice regarding which CAD software to teach and the most effective pedagogical methods [2]. This complexity is further compounded by the dynamic nature of software development and the diverse career paths of students, each demanding a distinct skill set for success. This intricate situation prompts the inquiry into an approach to future-proof and tailor CAD software education to the unique requirements of each student cohort . Perhaps the same tool that advances learning can be used for future-proofing? Whilst there are examples of successful uses of AI in education in other disciplines, the inquiry using baseline data from undergraduate and postgraduate students at a world leading institution raises additional questions: • Can we design an AI tool that develops bespoke CAD learning for students? • Can this learning go beyond simple command instructions and extract higher universal principles of CAD theory? • Specifically in HE, can AI be used to create individual learning plans based on student’s interests, industry needs and ongoing advances in CAD? References : [1] Brink, Kilbrink & Gericke, 2023. Teach to Use CAD or through Using CAD: An Interview Study with Technology Teachers. International journal of technology and design education 33.3: 957–979. [2] Xie, 2018. Learning and Teaching Engineering Design through Modeling and Simulation on a CAD Platform. Computer applications in engineering education 26.4: 824–840. [3] Ye, Peng, Chen & Cai, 2004. Today's students, tomorrow's engineers: an industrial perspective on CAD education, Computer-Aided Design, Volume 36, Issue 14, 2004, 1451-1460.

Applying geometric and dimensional tolerances (GD&T) to part features in computer-aided design (CAD) software is essential so that the part will function properly and to guide downstream manufacturing and inspection processes. However, it is not well characterized how CAD software implements capabilities for a designer to apply GD&T to a part. Of course, CAD software vendors do their own internal testing of those capabilities and users evaluate CAD software so that it satisfies their CAD modeling requirements. However, there has never been any rigorous public-domain testing of CAD software GD&T implementations. To improve that situation, the National Institute of Standards and Technology (NIST) has developed a system to test implementations of GD&T in CAD software. Representative part geometry with GD&T applied to features was modeled in four of the major CAD systems. Errors with semantic representation and graphical presentation of the GD&T were collected and analyzed. The testing methodology, test results, and data analysis demonstrate how well the CAD system GD&T implementations perform. The testing project results can be used as a basis for future testing, methods, and standards to evaluate defects in GD&T applied to part features.

Chapter 10 - Programmable Logic Devices

Evaluation of the virtual cement gap parameter of different CAD software programs in designing a single crown restoration: An in vitro study

This paper describes a methodology for automation of measurements in Computer-Aided Design (CAD) software by enabling the use of supervised learning algorithms. The paper presents a proof of concept of how dimensions are placed automatically in the drawing at predicted positions. The framework consists of two trained neural networks and a rule-based system. Four steps compound the methodology. 1. Create a data set of labeled images for training a pre-built convolutional neural network (YOLOv5) using CAD automatic procedures. 2. Train the model to make predictions on 2D drawing imagery, identifying their relevant features. 3. Reuse the information extracted from YOLOv5 in a new neural network to produce measurement data. The output of this model is a matrix containing measurement location and size data. 4. Convert the final data output into actual measurements of an unseen geometry using a rule-based system for automatic dimension generation. Although the rule-based system is highly dependent on the problem and the CAD software, both supervised learning models exhibit high performance and reusability. Future work aims to make the framework suitable for more complex products. The methodology presented is promising and shows potential for minimizing human resources in repetitive CAD work, particularly in the task of creating engineering drawings.

Rapid evolution of programmable logic device (PLD) architectures and the increasingly demanding requirements to meet with high-density and high-performance PLD designs call for a new generation of PLD synthesis tools to support many important capabilities not available in the existing synthesis tools. In this paper, we analyze the synthesis challenges and opportunities in supporting next-generation high-performance and high-density PLDs. We classify these challenges into two categories: (i) those implied from the advance of PLD architectures, including synthesis for hierarchical architectures and synthesis for heterogeneous architectures, and (ii) those driven by the requirements for high-density and high-performance PLD designs, including layout-driven synthesis, incremental synthesis, and IF-based synthesis. We shall discuss existing and/or potential solutions to these problems and outline research opportunities and directions for the development of next-generation PLD synthesis systems.

This study set out to compare the three-dimensional (3D) trueness of crowns produced from three types of lithium disilicate blocks. The working model was digitized, and single crowns (maxillary left second molar) were designed using computer-aided design (CAD) software. To produce a crown design model (CDM), a crown design file was extracted from the CAD software. In addition, using the CDM file and a milling machine (N = 20), three types of lithium disilicate blocks (e.max CAD, HASS Rosetta, and VITA Suprinity) were processed. To produce a crown scan model (CSM), the inner surface of each fabricated crown was digitized using a touch-probe scanner. In addition, using 3D inspection software, the CDM was partitioned (into marginal, axis, angular, and occlusal regions), the CDM and CSM were overlapped, and a 3D analysis was conducted. A Kruskal–Wallis test (α = 0.05) was conducted with all-segmented teeth with the root mean square (RMS), and they were analyzed using the Mann–Whitney U-test and the Bonferroni correction method as a post hoc test. There was a significant difference in the trueness of the crowns according to the type of lithium disilicate block (p < 0.001). The overall RMS value was at a maximum for e.max (42.9 ± 4.4 µm), followed by HASS (30.1 ± 9.0 µm) and then VITA (27.3 ± 7.9 µm). However, there was no significant difference between HASS and VITA (p = 0.541). There were significant differences in all regions inside the crown (p < 0.001). There was a significantly high trueness in the angular region inside the crown (p < 0.001). A correction could thus be applied in the CAD process, considering the differences in the trueness by the type of lithium disilicate block. In addition, to attain a crown with an excellent fit, it is necessary to provide a larger setting space for the angular region during the CAD process.

The article discusses why only programmable handheld devices can do the job of any 10 different gizmos. The development of a chameleon-like handheld device is also described. The programmable logic device (PLD), a semiconductor containing a personalization memory and logic elements, can make it possible to have a pocket-electronics device consolidated with a number of features including adaptability to any network, capability to fit new standards, and having an upgradeable security system for the latest virus. Conventional PLDs are big, slow, power hungry, and expensive, but, like the microprocessors, PLDs can evolve in time into higher-level logic primitives that make them suitable for untethered applications.

An Interactive Computer-aided Process Controller Design Package

This study investigates the impact of Project Based Learning (PBL) integrated with Computer Aided Design (CAD) software on improving technical drawing skills among vocational high school students. The experimental design involved two groups: an experimental group that received PBL based instruction using CAD software, and a control group that followed traditional instructional methods. The results revealed a significant improvement in the technical drawing skills of the experimental group, as indicated by higher post-test scores compared to the control group. These findings suggest that PBL, when coupled with CAD tools, fosters active learning, critical thinking, and enhances students' ability to visualize and create accurate technical drawings. Additionally, the project-based approach promoted collaboration, real world problem solving, and digital literacy, key competencies in vocational education. The study also identified a substantial effect size (Cohens d=2.97), emphasizing the significant educational impact of the PBL CAD integration. Despite the promising results, the study highlights limitations in terms of generalizability due to the single school sample and suggests further exploration of affective and behavioral outcomes in future research. In conclusion, the integration of PBL and CAD software represents an effective pedagogical strategy for improving technical drawing skills and preparing students for the demands of the modern workforce.

With growth demands to untethered embedded systems, e.g. sensor nodes, in the flexibility, performance, product longevity, areas, and decreasing time-to-market (TTM), programmable logic devices may allow covering lack of suitable processing units. Decrease in the feature transistor sizes allows producing smaller programmable devices and providing more computational power. However, such shrinking of feature sizes introduces higher power lost (static power). Moreover, programmable devices are clocked with higher frequencies due to the performance demands increase that introduces additional power consumption. Therefore, there is a need for techniques that allow for substantial power reduction and being achievable on the higher levels of the designing process. In this paper, we address means of the dynamic power consumption reduction on the system-level. This is envisaged that proposed techniques may allow achieving substantial power consumption savings with negligible hardware overheads while maintaining the energy per operation.

Objectives. Pipelining is an effective method for increasing the clock frequency of digital circuits. At the same time, balancing the pipeline stages during circuit synthesis at the register transfer level does not yet guarantee a balanced topological implementation of such a pipeline in terms of signal propagation delays according to the selected technological basis. This is due to the specifics of the algorithms for placing and routing components of digital devices, which are not capable of optimizing solutions in a strict mathematical sense in an acceptable time. In practice, approaches for developing digital devices combine manual control of topological constraints that set general rules for placing components with automatic optimization for localized fragments of the circuit are used to obtain results close to optimal. Pipeline circuits are based on a simple connection diagram of individual stages to demonstrate the effect of using topological design constraints on their example. On the basis of pipeline structures, a number of algorithms can be implemented to effectively complement programmable processor devices and provide hardware acceleration of some tasks. The present work develops methodological recommendations for managing topological design constraints in the implementation of pipeline computing structures based on programmable logic devices (PLD) with field-programmable gate array (FPGA) architecture.Methods. The work is based on accepted methods for designing and modeling digital systems.Results. Based on the analysis, modifications to a 32-bit CORDIC transcendental function computation pipeline were developed. By adding design constraints on the placement of register groups corresponding to the pipeline stages a significant increase in the clock frequency can be achieved as compared to automatic placement to reduce the running time of the tracing algorithms. The resulting effect is systematically reproduced in several implemented versions of the pipeline. Conclusions. The presented recommendations can be used to control the clock frequency and number of stages of pipeline computing structures while simultaneously reducing the time of one iteration and routing of a module based on PLD with FPGA architecture.

Additive manufacturing has opened the door to the creation of lightweight lattice structures. However, present Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) software are unsuitable for these types of structures. The objective of this research is to examine the performances of current CAD and CAE software to design lattice structures and to demonstrate their limitations and propose requirements for future developments. A performance evaluation of a case study for lattice structure designs was conducted. The criteria used for the evaluation were CAD human-machine-interface, RAM consumption, data exchange between CAD, CAE and CAM tools and finite element analysis (FEA) duration and file sizes. The CAD tool was incapable of executing a repetition function for octet-truss lattice structures of 150 x 150 x 150 mm dimensions or larger and the software stopped working. For 70 × 70 × 70 mm octet-truss lattice structure, the FEA computation file size reached 36.6 GB. The CAD file size of a 200 x 200 x 200 mm octet-truss lattice structure reached nearly 290 MB. In conclusion, this study exposes the performance inadequacy of current CAD and CAE tools and CAD file formats to design lattice structures for additive manufacturing parts.

This paper describes a structural design system for 3D drawing dies based on functional features using a minimum set of initial information. In addition, it is also applicable to assign the functional features flexibly before accomplishing the design of a solid model for the main parts of a drawing die, such as upper die, lower die, and blank holder. The initial information includes blank sizes, work strokes, die faces, punch open lines, and press data. The proposed system integrated the design knowledge of drawing die into functions of 3D computer-aided design (CAD) software to automate design and to shorten design time. This design system is constructed on a PC and integrated with a Pro/ENGINEER CAD system including feature selector, shape calculator, model generator, design coordinator, and user interface. The proposed system is demonstrated using the example of designing a drawing die for the roof panel of a vehicle within 1 h. The results reveal that it can dramatically improve the design quality and can save both time and costs with excellent design quality.