Go reconfigure [programmable logic in handheld devices

Advent of VLSI technology has paved the way for Programmable Logic Devices (PLD), which are widely used as the basic building blocks in high integrity electronic systems. PLDs are considered for their robust features such as high gate density, performance, speed etc. For PFBR Instrumentation and Control systems, PLDs are extensively used to implement digital designs such as VME bus interface logic, control logic and sequencing logic etc. Types of PLDs, such as Field Programmable Gate Arrays, Complex Programmable Logic Devices and Gate Array Logic devices are used in Core Temperature Monitoring System and Safety logics of shutdown systems. Since these devices are reliable as per the manufacturer's specification, they were used in R & D facilities like Fast Breeder Test Reactor and Augmented Boron Enrichment Plant as test beds. However, in order to use PLDs in commercial Nuclear Power Plant (in PFBR), it is vital to know about their performance in other critical applications. The availability of required data is limited, other than for space applications. So, it is proposed to conduct Quantitative Accelerated Life Tests (QALT) for the PLDs. QALT is designed to produce the data required for accelerated life data analysis. This analysis method uses life data obtained under accelerated conditions to extrapolate an estimated probability density function for the product under normal use conditions. Accelerated life tests are conducted on products to understand their failure modes and life characteristics. The products are subjected to enhanced stresses in order to force the products to fail early than they would normally, under use conditions. This process reduces test time. This paper discusses the methodology adapted to perform the Accelerated Life Test for the above mentioned PLDs.

Chapter 10 - Programmable Logic Devices

Digital design classes are increasingly using programmable logic devices (PLD) to augment the educational experience. Previous works discuss the advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), in digital logic design education and highlight the instructorpsilas experience of integrating these teaching methods in the classroom. This paper instead focuses on the studentspsila experience to determine the overall effectiveness of using PLD boards. By using statistics from a comprehensive survey that targets student feedback and opinion, and by comparing our classpsilas final exam scores with a previous class that did not use PLDs, we are able to informatively assess the benefits of using PLDs for digital design education.

Computer-aided design (CAD) software for programmable logic devices (PLDs) provides the link between design for programmable logic and the fuse pattems required to program the devices. This article reports an investigation into the current state of CAD support for PLDs. The study was necessary background to defining the requirements of a logic synthesis system for PLDs. Aspects of PLD CAD systems of particular relevance are the specification languages and capabilities of the packages. These directly relate to components of the synthesis system and its output format. The article attempts to provide recommendations and conclusions with regard to this.

Digital electronics is core curriculum in electronics and electrical engineering degrees. Programmable logic has now become its dominant implementation technology. We describe an integrated framework of practical work to support conventional (taught) design material, at all stages of an undergraduate degree course. Logic gate functions and state machines are first illustrated with demonstration units based on Programmable Logic Devices (PLDs). Students then use ABEL - a simple HDL (Hardware Description Language) - to implement a series of designs based around counters and state machines. A design exercise early in the second year requires students to use VHDL (VHSIC Hardware Description Language) to control a model lift with a simple FPGA (Field Programmable Gate Array), extending programmable implementation as well as programming language. Later work in the second year includes intensive team design projects involving programmable logic, and the design and test of a CMOS Gate Array system. All students therefore acquire transferable HDL skills. These can be developed further in the third year individual design project, where a range of HDL systems is available and it is easier to provide relatively expensive software for the limited numbers concerned. PLD programming is supported in two distinct ways. Conventional stand-alone programming stations provide for EPROMs and many PLDs, while in-system programming of standard architectures avoids bottlenecks in whole-class exercises. Hence, students are exposed to appropriate implementation technology in a manner suited to each level of their degree programme, to prime them well with transferable skills for their professional engineering careers.

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

Rapid evolution of programmable logic device (PLD) architectures and the increasingly demanding requirements to meet with high-density and high-performance PLD designs call for a new generation of PLD synthesis tools to support many important capabilities not available in the existing synthesis tools. In this paper, we analyze the synthesis challenges and opportunities in supporting next-generation high-performance and high-density PLDs. We classify these challenges into two categories: (i) those implied from the advance of PLD architectures, including synthesis for hierarchical architectures and synthesis for heterogeneous architectures, and (ii) those driven by the requirements for high-density and high-performance PLD designs, including layout-driven synthesis, incremental synthesis, and IF-based synthesis. We shall discuss existing and/or potential solutions to these problems and outline research opportunities and directions for the development of next-generation PLD synthesis systems.

A scheme for programmable logic array (PLA) decomposition that consists of one level of PLAs followed by a second level of simple two-input logic gates is presented. The propagation delay is therefore the sum of the delay through one level of PLA and one level of two-input gates. Since the delay through a two-input gate is significantly less than that through a PLA, the timing performance of the new scheme is generally superior to those of earlier PLA decomposition schemes. The sizes of the PLAs used depend on the choice of the two-input gates. An algorithm is presented that chooses the functionality of the gates such that the areas of the first-level PLAs are minimized, further improving performance. The new decomposition scheme was developed for the automatic programming of a programmable logic device (PLD) which had basically a three level architecture. The functional unit for such a PLD is described and the application of the algorithm to the programming of these functional units is discussed. Experimental results show that the new scheme significantly reduces the area over the single PLA implementation. >

Set operation is of great immediate significance in the PLD design. Using the set instead of several signals and constants can simplify a logical design. Most designers have paid attention to it, but they often neglect to use the set operation property further to simplify a design. This paper lists some rules of the set operation in use. By the practical design examples, it shows the way to use these rules of the set operation to simplify the PLD design. In the programmable logic device (PLD) design, the set operation property can simplify a logical design, and you will obtain an unexpected effect. Set is a group of signals or constants, which can execute operation of the whole. For example, Q=[Q3,Q2,Q1,Q0], where Q is a set that contains four elements. By using the set instead of several signals and constants in the PLD design, we can simplify a logical design and a description of the test vectors.

Objectives. Pipelining is an effective method for increasing the clock frequency of digital circuits. At the same time, balancing the pipeline stages during circuit synthesis at the register transfer level does not yet guarantee a balanced topological implementation of such a pipeline in terms of signal propagation delays according to the selected technological basis. This is due to the specifics of the algorithms for placing and routing components of digital devices, which are not capable of optimizing solutions in a strict mathematical sense in an acceptable time. In practice, approaches for developing digital devices combine manual control of topological constraints that set general rules for placing components with automatic optimization for localized fragments of the circuit are used to obtain results close to optimal. Pipeline circuits are based on a simple connection diagram of individual stages to demonstrate the effect of using topological design constraints on their example. On the basis of pipeline structures, a number of algorithms can be implemented to effectively complement programmable processor devices and provide hardware acceleration of some tasks. The present work develops methodological recommendations for managing topological design constraints in the implementation of pipeline computing structures based on programmable logic devices (PLD) with field-programmable gate array (FPGA) architecture.Methods. The work is based on accepted methods for designing and modeling digital systems.Results. Based on the analysis, modifications to a 32-bit CORDIC transcendental function computation pipeline were developed. By adding design constraints on the placement of register groups corresponding to the pipeline stages a significant increase in the clock frequency can be achieved as compared to automatic placement to reduce the running time of the tracing algorithms. The resulting effect is systematically reproduced in several implemented versions of the pipeline. Conclusions. The presented recommendations can be used to control the clock frequency and number of stages of pipeline computing structures while simultaneously reducing the time of one iteration and routing of a module based on PLD with FPGA architecture.

With growth demands to untethered embedded systems, e.g. sensor nodes, in the flexibility, performance, product longevity, areas, and decreasing time-to-market (TTM), programmable logic devices may allow covering lack of suitable processing units. Decrease in the feature transistor sizes allows producing smaller programmable devices and providing more computational power. However, such shrinking of feature sizes introduces higher power lost (static power). Moreover, programmable devices are clocked with higher frequencies due to the performance demands increase that introduces additional power consumption. Therefore, there is a need for techniques that allow for substantial power reduction and being achievable on the higher levels of the designing process. In this paper, we address means of the dynamic power consumption reduction on the system-level. This is envisaged that proposed techniques may allow achieving substantial power consumption savings with negligible hardware overheads while maintaining the energy per operation.

A family of user-programmable peripherals, utilizing an integration strategy based on a programmable system device (PSD) concept, is described. Specifically, PSD is an efficient and highly configurable integration of high-density memory and LSI level logic blocks. The configurability is derived by providing programmable logic and programmable interconnect. PSDX is the first PSD family of programmable microcontroller peripherals; it integrates 256 kb to 1 Mb of EPROM, 16 kb of SRAM, a 28-input by 42-product term programmable logic device (PLD), and flexible I/O ports. This family is primarily targeted for embedded microcontroller applications. Using one PSD device it is possible to replace all the core peripherals in the system and, as a result, achieve a reduction in components, power dissipation, and overall system cost. The flexible architecture is achieved by providing 46 configuration options, which allows the PSD to interface with virtually any 8- or 16-b microcontroller. The integration is made possible by developing a special configurability and testability scheme. These parts are realized on a 1.2- mu m CMOS EPROM process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ABSTRACTThe tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

Deep Neural Networks are becoming the de-facto standard models for image understanding, and more generally for computer vision tasks. As they involve highly parallelizable computations, CNN are well suited to current fine grain programmable logic devices. Thus, multiple CNN accelerators have been successfully implemented on FPGAs. Unfortunately, FPGA resources such as logic elements or DSP units remain limited. This work presents a holistic method relying on approximate computing and design space exploration to optimize the DSP block utilization of a CNN implementation on an FPGA. This method was tested when implementing a reconfigurable OCR convolutional neural network on an Altera Stratix V device and varying both data representation and CNN topology in order to find the best combination in terms of DSP block utilization and classification accuracy. This exploration generated dataflow architectures of 76 CNN topologies with 5 different fixed point representation. Most efficient implementation performs 883 classifications/sec at 256 x 256 resolution using 8% of the available DSP blocks.

This paper discusses a 3.3 V programmable logic device family which provides up to 130 Kgates. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 6,656 logic elements and circuit techniques to address low power supply and interface trends. It is designed on a 0.35 /spl mu/m triple metal-dual oxide process to operate in a 3.3 V only, 5 V only or 3.3 V-5 V systems. Under worst case operating conditions it was observed to have a typical system operating frequency of 90 MHz. The EPF10K50V is the first member of the second-generation FLEX 10K family.