Design Automation Framework for Reconfigurable Interconnection Networks

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.

A Computer Aided Design (CAD) tool consisting of two new interconnect network routing algorithms is developed. It was developed to assist in manufacturing test development for any Programmable Logic Device (PLD) such as Complex Programmable Logic Devices (CPLDs) and/or Field Programmable Gate Array (FPGA) devices which utilize any interconnect network structure whose definition/connectivity and control can be described in a presented manner. The CAD tool utilizing the new routing algorithms supports manual and semiautomatic explicit, non-explicit, and net routing and was extensively tested on the interconnect networks of the Cypress Delta39K/sup TM/ series CPLD for the purpose of manufacturing testing of the programmable interconnect networks within the device as well as all programmable logic functions of the device. The two routing algorithms were developed and experimentally proved to work correctly with the best one chosen based on both theoretical and experimental complexity analysis and the particular routing scenario to be solved. The resultant routing CAD tool will produce the configuration bits necessary to program or configure PLD devices for the extensive tests that must be applied to ensure that the manufactured PLDs are defect-free. The router CAD tool can also be extensively used in the verification of the design process of PLDs as verified via experimental testing.

According to some casual observers, computer-aided design (CAD) tools are very similar. These tools are used to design new artifacts in a digital environment; hence, they share typical software components, such as a computing engine and human–machine interface. However, CAD software is dedicated to specific professionals – such as engineers, three-dimensional (3D) artists, and industrial designers (IDs) – who claim that, despite their apparent similarities, CAD tools are so different that they are not substitutable. Moreover, CAD tools do not fully meet the needs of IDs. This paper aims at better characterizing CAD tools by taking into account their underlying design logic, which involves relying on recent advances in design theory. We show that engineering CAD tools are actually modeling tools that design a generic variety of products; 3D artist CAD tools not only design but immediately produce single digital artifacts; and ID CAD tools are neither a mix nor an hybridization of engineering CAD and 3D artist CAD tools but have their own logic, namely to create new conceptual models for a large variety of products, that is, the creation of a unique original style that leads to a generic singularity. Such tools are useful for many creative designers beyond IDs.

The frame transfer Area Array Sensor with vertical antiblooming structure requires that all performance characteristics such as large charge capacity, high charge transfer efficiency, low read noise and low antiblooming voltage be optimized in a singlemanufacturable CCD (charge-coupled device). There is a common tendency to optimize one performance characteristic at the expense of others. With the goal of optimizing above all performance characteristics, a frame transfer area array sensors with vertical antiblooming structure is optimization designed by the CAD (computer aided design) tools and fabricated, which equal to twenty-six micron square pixel size with 516 (H) x1028 (V) active pixels(the channel stop is 4μm and the photosensitive area is 22x22 μmxμm). At first, it is simply introduced the modeling of the frame transfer area array sensors with vertical antiblooming structure from the top to down and simulated by the CAD tools combined with the process and device models. The essential design and calculation of the CCD with antiblooming function are discussed in detail. And the process, layout and device parameters to design this frame transfer area array sensors (including the impurity concentration and layer thickness of the P-well and the buriedchannel, and the design output amplifier) are optimized according to the above simulation. At the last, the device is fabricated and the performance characteristics ( e.g. charge capacity, charge transfer efficiency, read noise and antiblooming voltage) are test to compare the simulation. To demonstrate the process used to optimize this frame transfer area array sensors with vertical antiblooming structure, this paper contains test data for this kind of CCD device which is optimization designed and fabricated by the CAD (computer aided design) tools. The test datas shows the way using the CAD tools optimization design a frame transfer area array sensors with vertical antiblooming structure correct.

Field Programmable Gate Arrays (FPGAs) have become a popular medium for the implementation of many digital circuits. Mapping applications into FPGAs requires a set of efficient Computer-Aided Design (CAD) tools to obtain high-quality Integrated Circuits (ICs). One critical issue of FPGA implementation is the quality and efficiency of associated CAD algorithms. In this paper, we are interested in investigating clustering algorithms aspect to optimize Mesh of Clusters (MoCs) FPGA performance. In fact, the way we distribute Logic Blocks (LBs) between FPGA clusters has an important impact on performance. In this paper, we explore the effects of two clustering algorithms (First Choice (FC) and T-VPack) on MoCs FPGA architecture based only on short routing wires. This paper highlights and experimentally demonstrates that FC clustering algorithm ameliorates power consumption, area, critical path delay and energy by an average of 17%, 11%, 13% and 24% respectively compared to T-VPack for MoCs FPGA.

This paper describes a parallel algorithm for the Euclidean distance transform on a special-purpose architecture based on a reconfigurable mesh interconnection network. The proposed architecture, which supports the Euclidean distance transform algorithm as well as other low-level image processing algorithms, is particularly interesting because it can be effectively implemented in hardware and it can be programmed at a high level. The Euclidean distance transform algorithm described in this paper exploits the specific features of the reconfigurable interconnection network of the proposed dedicated architecture and takes advantage of the natural matching both between the data structure of the problem (a mesh of pixels) and that of the dedicated architecture (a mesh of processing elements) and between the nature of the computation (distance computation) and the capability of the interconnection network to let information flow from one node to a set of nodes by means of reconfigurable buses. The proposed algorithm has been implemented and has been validated through simulation, its computational complexity is O(N) (worst case) for pictures of N/spl times/N pixels on an architecture with N/spl times/N processing elements.

Additive manufacturing has opened the door to the creation of lightweight lattice structures. However, present Computer-Aided Design (CAD) and Computer-Aided Engineering (CAE) software are unsuitable for these types of structures. The objective of this research is to examine the performances of current CAD and CAE software to design lattice structures and to demonstrate their limitations and propose requirements for future developments. A performance evaluation of a case study for lattice structure designs was conducted. The criteria used for the evaluation were CAD human-machine-interface, RAM consumption, data exchange between CAD, CAE and CAM tools and finite element analysis (FEA) duration and file sizes. The CAD tool was incapable of executing a repetition function for octet-truss lattice structures of 150 x 150 x 150 mm dimensions or larger and the software stopped working. For 70 × 70 × 70 mm octet-truss lattice structure, the FEA computation file size reached 36.6 GB. The CAD file size of a 200 x 200 x 200 mm octet-truss lattice structure reached nearly 290 MB. In conclusion, this study exposes the performance inadequacy of current CAD and CAE tools and CAD file formats to design lattice structures for additive manufacturing parts.

Following the vision of Industry 4.0, manufacturers started to break down products into subsystems, each of which is developed and supplied by different suppliers to tackle the increasing complexity of product development (e.g., in vehicle, machine or plant construction). This process needs to be supported by intuitive Computer-Aided Design (CAD) tools and virtual modeling and simulation environments to effectively meet the challenges of increasingly complex product development. Therefore, in this paper, we present some outcoming of a research project called DisMoSim ( Dis tributed Mo deling and Sim ulation), which proposes an intuitive virtual environment for modeling and simulation that embeds a Multi User Inverse Kinematic Solver (MUKS). The MUKS allows (i) individual subsystems to be tested intuitively, i.e., Rapid Testing (RT), and (ii) people not yet familiar with a subsystem to understand it easily and quickly through simple kinematic actions, i.e., Rapid Understanding (RU), without unnaturally interrupting the modeling process. Finally, (iii) the MUKS enables subsystems to be easily assembled into complete systems, i.e., Rapid Assembling (RA), by means of a so-called snapping-point mechanism which supports the complex process of aligning and assembling different subsystems. To evaluate these capabilities, we present the results of a user study conducted with 20 participants. Special attention has been given to the embedded MUKS in contrast to existing approaches known from common CAD and simulation software. Thus, we demonstrate the practicability, usability, and versatility of our approach. • Finding modeling and simulation errors in CAD models is cumbersome with current tools. • CAD tools need intuitive means for testing during modeling. • Inverse kinematic solvers allow for rapid prototyping and testing in CAD systems. • New user interface and interaction paradigms ease interaction with CAD tools.

Managing leakage power in field programmable gate arrays (FPGAs) has become critical for the FPGA industry to remain competitive in the semiconductor market and enter the mobile applications domain. This paper proposes and evaluates several dual-Vt-based designs of FPGA architecture for reducing the leakage power. A dual-Vt FPGA computer-aided design (CAD) framework has been proposed, which is used to develop and evaluate different dual-Vt FPGA architectures. The logic elements and the routing resources are considered as candidates for dual-Vt assignment. The authors estimate the number of the logic elements that can be assigned as high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework. Based upon this estimate, the authors develop and evaluate two kinds of architectures, homogenous and heterogenous. The results indicate that an average leakage-power savings of up to 50% can be obtained from these architectures. This CAD framework can also be used for developing and evaluating different dual-Vt FPGA architectures other than the ones proposed in this paper

Recently, digital Intermediate Frequency (IF) waveform generators and receivers are introduced in modern radar systems to reduce the cost, size, and achieve better performance. Moreover, digital IF waveform generators achieve the requirements of high resolution and complex modulation schemes. Digital receivers have better sensitivity, wider dynamic range and lower noise Figure than analog receivers. Digital IF waveform generators and receivers work well in conjunction with a high-speed Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC). In this paper, the design and implementation of high-speed data acquisition circuits (ADC and DAC) to generate and acquire IF waveforms are presented. Different modulated waveforms are generated digitally using Field Programmable Gate Array (FPGA). The corresponding digital receiver, including digital phase detection and matched filtering, is designed and implemented on the same FPGA chip. Design and implementation of a Printed Circuit Board (PCB) including FPGA chip and its required circuitry are introduced. The proposed design is simulated using Computer-Aided Design (CAD) tools and verified experimentally through laboratory testing.

One way to enhance students’ ability to visualize 3-D objects is to make their experience of the objects, while learning, as realistic as possible. However, in general, it is very difficult to clearly describe to students a 3-D object and the spatial relationship between the object components, without using a physical mockup. Physical mockups take a lot of time to construct, especially for more complex objects. As a result, graphics educators have started to use 3-D computer-aided design (CAD) tools to help students understand the spatial relationships between objects. However, CAD tools only allow students to examine 3-D models from outside flat computer monitors. In other words, the models and the viewers are in different realms. Using traditional CAD tools, students cannot view models with natural stereoscopic vision. Virtual reality (VR) is a computer technology of simulating or replicating a physical environment to give users a sense of being there, taking control, and physically interacting with the environment (Ausburn & Ausburn, 2004). VR technology breaks down barriers between humans and computers by immersing viewers in a computer-generated stereoscopic environment. With advances in hardware and software, most PC computers now have the capability to support VR use. Thus, VR has now become an affordable visualization tool that can be used in classrooms. As Ausburn and Ausburn (2004) indicated, there is a significant opportunity to expand and explore the use of VR in classrooms. Research suggests that VR is an effective tool that enhances learning in areas such as engineering (Sulbaran & Baker, 2000). In addition, VR engages the intellectual, social, and emotional processes of learners. The impact of VR is due to its ability to encourage interaction and ability to motivate learners (Winn et al., 1997). Salzman (1999) found that VR applications in education depends on VR features, class contents, students’ characteristics, and students’ prior experiences. The emphasis of engineering graphics education has been placed on design, problemsolving, presentation, and communication skills. Three dimensional spatial visualization ability is the core requirement for successfully developing those skills. The use of VR may also represent an effective strategy that supports the development of spatial skills. It is important to combine exposure to VR models with activities such as sketching or drawing as a means for developing a capacity for visual imagery and creativity (Deno, 1995; Devon et al., 1994; Sorby, 1999). Sorby (1999) explained that in most cases, graphics curricula begin with multi-view sketching/drawing and then move to pictorial sketching. However, this

Besides foundry facilities, Computer-Aided Design (CAD)tools are also required to move microsystems from researchprototypes to an industrial market. Currently available CADtools need extensions before they can be used for theautomated design of micromachined devices.This paper presents a low cost access to microsystemtechnology (MST), applied by the CMP service, and based onthe use of existing microelectronics production lines, withadditional post-processing for microsystem specific 2D and3D structures, and a global CAD approach for the design andsimulation of microsystems applied to currently availablecommercial CAD tools, e.g. Mentor Framework, in order toensure a continuous flow from the design to themanufacturing.

The expanded use of field programmable gate arrays (FPGA) in remote, long life, and system-critical applications requires the development and implementation of effective, efficient FPGA fault-tolerance techniques. FPGA have inherent redundancy and in-the-field reconfiguration capabilities, thus providing alternatives to standard integrated circuit redundancy-based fault-recovery techniques. Runtime reliability can be enhanced by using such unique features. Recovery from permanent logic and interconnect faults without runtime computer-aided design (CAD) support can be efficiently performed with the use of fine-grained and physical design partitioning. Faults are localized to small partitioned blocks that have fixed interfaces to the surrounding portions of the design, and the affected blocks are reconfigured with previously generated, functionally equivalent block instances that do not use the faulty resources. This technique minimizes the post-fault-detection system downtime, while requiring little area overhead. Only the finely located faulty portions of the FPGA are removed from use. In addition, the end user need not have access to CAD tools, making the algorithm completely transparent to system users. This approach has been efficiently implemented on a diverse set of FPGA architectures. The algorithm's flexibility is also apparent from the variable emphases that can be placed on system reliability, area overhead, timing overhead, design effort, and system memory. Given user-defined emphases, the algorithm can be modified to specific application requirements. Experiments using random s-independent and s-correlated fault models reveal that the approach enhances system reliability, while minimizing area and timing overhead.

In this paper, aiming at the problems of difficult positioning, slow speed and low precision of digital printing, a detection system suitable for textile printing positioning is proposed and designed. This detection system innovatively combines a neural network and field programmable gate array (FPGA) to realize rapid and accurate positioning of printing. In the neural network part, this paper selects the backbone network Darknet19 of YOLOv2 as the backbone network, and under the premise of ensuring a certain detection accuracy, the network model is pruned and quantified to make it suitable for deployment on the embedded device FPGA. In addition, before the network training, this paper optimizes the candidate boxes by introducing k-means clustering to customize the analysis of the fabric print dataset to improve the detection accuracy. In the FPGA part, this paper optimizes the architecture on the FPGA side in two parts: data computation and data transmission. In terms of computational optimization, parallel optimization of the neural network is performed by combining FPGA optimization methods, such as pipeline and unroll. In terms of transmission optimization, we use a double-buffered design to ping-pong in the input and output modules to overlap the latency, and then use multi-port transmission to improve the overall bandwidth utilization and reduce the transmission latency caused by on-chip and off-chip interactions. The experimental results show that the detection system combining the neural network and FPGA can effectively position fabric prints and meet the needs of real-time. The design scheme has lower power compared to the graphics processing unit and is faster compared to the central processing unit.

Hardware acceleration using field programmable gate arrays (FPGAs) has become increasingly popular for computationally intensive digital signal processing (DSP) applications. Unfortunately, while FPGAs have a reasonably tractable computer aided design (CAD) flow and performance, they have poor power characteristics when compared to direct application specific integrated circuit (ASIC) fabrication. ASICs exhibit better performance and power than FPGAs, but require complex CAD and large non-recurring engineering (NRE) costs. A reconfigurable device that exhibits ASIC-like power characteristics and FPGA-like costs and tool support is desirable to fill this void. Several coarse-grained fabric architectures proposed during the last decade have been focused on performance and area-efficient architectural techniques. Even though power is becoming one of the critical design concerns for semiconductor industry, this issue has not been adequately addressed in the existing coarse-grained fabric architectures. In this paper, a low-power and high-performance hardware acceleration engine for DSP style applications is described. This reconfigurable fabric model is generic and parameterizable allowing design parameters to be adjusted within the architecture. The impact of varying different design parameters such as functional unit granularity, and multiplexer cardinality are studied for their implications on power and performance. The low-power fabric was designed to operate within the SuperCISC processor architecture designed at the University of Pittsburgh