- Conference Article
13
- 10.5555/198174.198306
Generating VHDL models from natural language descriptions
- Sep 23, 1994
- Walling R Cyre + 3 more +3
This paper describes two approaches to the automatic generation of behavioral VHDL models from descriptions written in natural language. Both approaches are based on a modeling style in which behavior is represented by a system of interconnected processes. The first approach employs a semantic grammar to directly generate a single VHDL process from a paragraph written in a restricted English called ModelSpeak. The second approach accepts more general English and generates models consisting of multiple processes. series of sentences describing the behavior of a single process and generated correct VHDL code for it. This interface requires the behavior be expressed in a highly restricted English called ModelSpeak (10). Conditional expressions (if statements) may be nested to two levels, and interaction is invoked by the interface to resolve scope ambiguity of loops. This interface is implemented with a semantic grammar (3) in Prolog. The second interface (Approach II) to the Modeler's Assistant for natural language is substantially more complex, but accepts more general English expressions and generates multiple-process models. In this approach, each sentence is parsed by a bottom-up, parallel chart parser to generate a set of valid parse trees. The trees are examined by a Semantic Analyzer (7) to determine one which is semantically correct, and a conceptual graph (14) (semantic network) of its meaning is generated. Once the conceptual graph of individual sentences are joined together (12), a program called the Linker (8) analyzes the graph to produce a Process Model Graph and VHDL process code for the Modeler's Assistant. Nodes in the conceptual graph representing verbs typically generate processes or the conditions which govern them. Nodes representing objects generate signals. The modeling style underlying the Linker produces a sizable collection of processes, each consisting of a single if_then statement. To avoid unnecessary bus resolutions, multiple processes assigning to the same signal are merged. Since signal types are generally not expressed in the English description, they may be added interactively later. Before describing the approaches in more detail, related research on natural language interfaces is reviewed briefly.
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