Concurrent error detection and correction in dual basis multiplier over GF(2 m )

Fault-based cryptanalysis has been developed to effectively break both private-key and public-key cryptosystems, making robust finite field multiplication a very important research topic in recent years. However, no robust normal basis multiplier has been proposed in the literature. Therefore, this investigation presents a semisystolic Gaussian normal basis multiplier. Based on the proposed Gaussian normal basis multiplier, both concurrent error detection and correction capabilities can be easily achieved using time redundancy technology with no hardware modification.

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

The concurrent error detection capability can give countermeasure to recent developed fault-based cryptanalysis. The design-for-testability is one of evaluated indexes to detect the faulty element of VLSI chips for manufacturability and maintainability issues. Thus, design of multipliers in GF(2m) with both concurrent error detection and design-for-testability is an important issue for elliptic curve cryptosystem. In this study, a novel self-checking alternating logic (SCAL) multiplier in GF(2m) is presented for achieving both on-line test and off-line test purposes. The proposed polynomial basis multiplier using irreducible trinomials requires only about 33% extra space complexity of existing multipliers. As our best knowledge, the proposed polynomial basis multiplier is the first polynomial basis multiplier which can provide both on-line error detection and off-line test capabilities.

Processors with concurrent error detection (CED) capability are called self-checking processors. CED is a very important and necessary feature in VLSI microprocessors that are integral and ultradependable for real-time applications. The design of self-checking reduced instruction set computer (RISC) requires the state-of-the-art techniques in computer architectures, implementation and self-checking designs.

This paper presents a VHDL-based methodology to design Self-Checking (SC) Finite State Machines (FSM). The methodology provides a library of pre-designed, parameterized concurrent error-detection (CED) modules as well as a VHDL code template that allow easily creation of synthesizable highlevel description of the SC FSM with minor additional design development time. The template offers selection of error-detecting schemes that will be used for encoding output data and states of the FSM. The generated SC FSM description can be simulated and synthesized with commercial tools. Effectiveness of the methodology is evaluated on a set of benchmark FSMs.

Emerging technologies are dealing with more complex VLSI systems, also smaller gates and transistors which are severely influenced by electromagnetic noises and single event transient (SET) errors. Because of this increase in sensitivity and decrease in size, several soft errors might appear at the same time which can lead to multiple simultaneous errors. In this paper a concurrent and multiple error detection and correction scheme is presented for adders and multipliers based on the combination of a parity prediction scheme and a partially distributed triple modular redundancy. This scheme fits carry look-ahead and carry-skip adders/ALUs in which the carry logic represents the largest part of the circuit. The efficiency of the scheme is basically analyzed by the probability computations. The simulation of multiple random fault injection is performed to validate the predicted performance.

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

The reliability of new SRAM FPGA (Field Programmable Gate Array) devices, which are the first components launched for each new generation of transistor, is difficult to estimate. Their increasing use on electronic boards in both terrestrial and space applications necessitates the development of fault tolerant techniques in the wake of growing soft error rates (SER). In this article, In this article, a concurrent error detection and correction scheme using residue codes is proposed and designed. The results express the gain for power consumption and circuit area compared for other solutions for fault detection or fault correction.

This work develops a novel self-checking alternating logic (SCAL) bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m). The proposed GNB multiplier is with both concurrent error-detection and off-line testing capabilities. The concurrent error-detection capability can give countermeasure to fault-based cryptanalysis. The off-line testing capability supports the design-for-test property. The proposed SCAL GNB multiplier can detect both permanent and transient faults. The proposed SCAL GNB is the first normal basis multiplier to have both on-line error-detection and off-line testing capabilities.

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

A floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%.

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.

This paper presents a concurrent error detection (CED) scheme for orthogonal Latin square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it is strongly fault secured for single stuck-at faults. Extensive simulation results are also provided; different figures of merit such as area, power dissipation, gate depth, and coverage are assessed. It is shown that the proposed decoder designs for ( n, k) t-bit error correcting OLS codes (k = 16 ...256; t = 2 ...5) have reasonable overhead; for example, the average area overhead of the proposed CED is 35.5 (23.6) % compared with an OLS decoder with no CED (i.e., the previously reported CED scheme). However, the most significant advantage of the proposed scheme is that it achieves 100% fault coverage for the whole CED circuit, thus providing a very efficient and fully fault-tolerant implementation. The proposed CED is applicable to both binary and nonbinary OLS codes; the CED for a nonbinary OLS decoder achieves comparable or better results than a binary OLS decoder. Moreover, simulation shows that the proposed CED scheme is better than double modular redundancy.