Concurrent Error Detection and Correction in Gaussian Normal Basis Multiplier over GF(2^m)

This work develops a novel self-checking alternating logic (SCAL) bit-parallel Gaussian normal basis (GNB) multiplier with type-t over GF(2m). The proposed GNB multiplier is with both concurrent error-detection and off-line testing capabilities. The concurrent error-detection capability can give countermeasure to fault-based cryptanalysis. The off-line testing capability supports the design-for-test property. The proposed SCAL GNB multiplier can detect both permanent and transient faults. The proposed SCAL GNB is the first normal basis multiplier to have both on-line error-detection and off-line testing capabilities.

Fault-based side-channel cryptanalysis is a useful technique against symmetrical and asymmetrical encryption/decryption algorithms. Thus, eliminating cryptographic computation errors become critical in preventing such kind of attacks. A simple way to eliminating cryptographic computation errors is to output correct or corrected ciphers. Multiplication is the most important finite field arithmetic operation in the cryptographic computations. By using time redundancy technique, a novel dual basis (DB) multiplier over Galois fields (2m) will be presented with lower space complexity and feedback-free property. Based on the proposed feedback-free DB multiplier, the DB multiplier with a concurrent error detection (CED) capability is also easily developed. Compared with the existing DB multiplier with CED capability, the proposed one saves about 90% of time-area complexity. No existing DB multiplier in the literature has concurrent error correction (CEC) capability. Based on the proposed DB multiplier, a novel DB multiplier with CEC capability is easily designed. The proposed DB multiplier with CEC capability requires only about 3% of extra space complexity and 15% of time complexity when compared with the proposed DB multiplier without CEC.

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation; data from the non-volatile memory element is copied back to the SRAM core. The dual-rail checker utilizes two XOR gates each made of 2 inverters and 2 ambipolar transistors, hence, it has a hybrid nature. Extensive simulation results are provided. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit such as delay and circuit complexity and thus applicable to integrated circuits such as FPGAs requiring secure on-chip non-volatile storage (i.e. LUTs) for multi-context configurability.

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

A systematic approach for designing concurrent error-detecting systolic arrays using redundancy

The concurrent error detection capability can give countermeasure to recent developed fault-based cryptanalysis. The design-for-testability is one of evaluated indexes to detect the faulty element of VLSI chips for manufacturability and maintainability issues. Thus, design of multipliers in GF(2m) with both concurrent error detection and design-for-testability is an important issue for elliptic curve cryptosystem. In this study, a novel self-checking alternating logic (SCAL) multiplier in GF(2m) is presented for achieving both on-line test and off-line test purposes. The proposed polynomial basis multiplier using irreducible trinomials requires only about 33% extra space complexity of existing multipliers. As our best knowledge, the proposed polynomial basis multiplier is the first polynomial basis multiplier which can provide both on-line error detection and off-line test capabilities.

Concurrent Error Detection (CED) methods are commonly employed to provide some level of error detection capability at the cost of some area and power overhead. In many applications, however, the error detection capability must be reconfigured dynamically, in order to adapt to the available power budget, criticality of the processed data, a thermal-safe schedule, etc. In this work, we propose a reconfigurable duplication-based CED infrastructure for logic circuits. The key idea is to enable/disable the operation of the duplicate circuit according to a set of control conditions. When CED is disabled, the inputs to the duplicate circuit retain their previous values (i.e., reduction in power dissipation via elimination of switching activity), yet errors are not detected (i.e., reduction in CED coverage). Experimental results using judicious and random selection of control conditions yield the same end-result; power dissipation is commensurate with CED coverage. Therefore, LFSR structures can be used to easily generate and reconfigure conditions, enabling their dynamic adjustment to adapt to the power constraints of the system.

Processors with concurrent error detection (CED) capability are called self-checking processors. CED is a very important and necessary feature in VLSI microprocessors that are integral and ultradependable for real-time applications. The design of self-checking reduced instruction set computer (RISC) requires the state-of-the-art techniques in computer architectures, implementation and self-checking designs.

Error correction coding, channel coding, also known as error control coding, is to add some redundant code elements, or check code elements, to form a correlated sequence of code elements—code words and to use the correlation property between code elements to detect and correct errors when decoding. Different error correction coding schemes have different error detection and correction capabilities. This paper designs a combination of parity check and cyclic redundancy check (CRC) to improve the error detection and correction capabilities with minimum cost, so that the system can transmit information more efficiently while also having high transmission reliability.

본 논문에서는 가우시안 정규기저를 갖는 유한체 <TEX>$GF(2^n)$</TEX>의 곱셈기 오류 탐지 방법을 제시한다. 제안하는 오류 탐지 방법은 하드웨어로 단순하게 구성된다. 즉 n-bit 출력 직렬 곱셈기에서는 1 개의 AND gate, n+1 개의 XOR gate, 그리고 1 개의 1-bit register로 구성되며, 병렬 곱셈기의 경우 n 개의 AND gate와 2n-1 개의 XOR gate로 구성된다. 제안하는 방법은 C=AB 연산에 홀수개의 오류가 발생하는 경우 탐지가 된다. In this paper, we proposed an error detection in Gaussian normal basis multiplier over <TEX>$GF(2^n)$</TEX>. It is shown that by using parity prediction, error detection can be very simply constructed in hardware. The hardware overheads are only one AND gate, n+1 XOR gates, and one 1-bit register in serial multipliers, and so n AND gates, 2n-1 XOR gates in parallel multipliers. This method are detect in odd number of bit fault in C = AB.

New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.

Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.

The reliability of new SRAM FPGA (Field Programmable Gate Array) devices, which are the first components launched for each new generation of transistor, is difficult to estimate. Their increasing use on electronic boards in both terrestrial and space applications necessitates the development of fault tolerant techniques in the wake of growing soft error rates (SER). In this article, In this article, a concurrent error detection and correction scheme using residue codes is proposed and designed. The results express the gain for power consumption and circuit area compared for other solutions for fault detection or fault correction.

This paper presents a VHDL-based methodology to design Self-Checking (SC) Finite State Machines (FSM). The methodology provides a library of pre-designed, parameterized concurrent error-detection (CED) modules as well as a VHDL code template that allow easily creation of synthesizable highlevel description of the SC FSM with minor additional design development time. The template offers selection of error-detecting schemes that will be used for encoding output data and states of the FSM. The generated SC FSM description can be simulated and synthesized with commercial tools. Effectiveness of the methodology is evaluated on a set of benchmark FSMs.

Recently, considerable research has been performed in cryptography and security to optimize the area, power, timing, and energy needed for the point multiplication operations over binary elliptic curves. In this paper, we propose an efficient implementation of point multiplication on Koblitz curves targeting extremely-constrained, secure applications. We utilize the Gaussian normal basis (GNB) representation of field elements over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) and employ an efficient bit-level GNB multiplier. One advantage of this GNB multiplier is that we are able to reduce the hardware complexity through sharing the addition/accumulation with other field additions. We utilized the special property of normal basis representation and squarings are implemented very efficiently by only rewiring in hardware. We introduce a new technique for point addition in affine coordinate which requires fewer registers. Based on this technique, we propose an extremely small processor architecture for point multiplication. Through application-specific integrated circuit (ASIC) implementations, we evaluate the area, performance, and energy consumption of the proposed crypto-processor. Utilizing two different working frequencies, it is shown that the proposed architecture reaches better results compared to the previous works, making it suitable for extremely-constrained, secure environments.