Constant-bandwidth supply for priority processing

This rapid advancement in digital technologies has significantly changed the organizational training and development practices and consequently heightened the use of virtual training platforms. Virtual training platforms use technology-enabled learning tools that include learning management systems, online modules, video conferencing, simulations and interactive content to offer flexible and scalable training solutions. The study explores the effect of a virtual training platform on the effectiveness of employee work, with a focus on productivity and job performance. The question is informed by a critical review of the literature, where virtual training is identified to be influential in promoting skill development, knowledge retention, adaptability and performance outcomes. The review of previous studies showed that virtual training platforms promote continuous learning, reduce training time and costs and ensure better transfer of learning to the workplace. Additional factors that could explain high engagement and improvement in job-related competencies include interactive features, real-time feedback and learner-centered design. Work effectiveness, operationalized in terms of productivity, task performance, adaptability and quality of work output, will be influenced by the extent to which training aligns with job requirements and organizational goals. The literature has shown a strong positive relationship between virtual platforms and employee productivity and job performance. Workers who have undergone training on virtual platforms are more efficient, solve problems more and feel more confident in performing their tasks. The study thus concludes that virtual training platforms serve as a strategic human resource development tool in modern organizations. When appropriately designed and integrated with performance management systems, virtual training significantly improves employee work effectiveness and leads to continued organizational competitiveness.

Automatic design space exploration (DSE) tools have been employed over years to evaluate high-performance computer architectures and software designs via on simulation tools. As today's smartphones and consumer electronic devices have become so complex, DSE tools are needed to speed up the design process and produce better designs for the targeted applications. However, traditional simulation tools are too slow to report good system designs in a timely fashion. Thus, in this paper, we propose a framework, called Android Design Space Exploration Tool (ADSET), to facilitate DSE for modern consumer electronic devices. To shorten the exploration time, we adopt a fast full-system modeling technique in our previous work and further develop a parallel DSE method to concurrently evaluate the multiple design points. In our case study, we show that ADSET is capable of modeling Android smartphones in the market and rapidly finds good designs in a large design space.

As the MEMS (Micro-Electro-Mechanical Systems) devices head towards smaller form factor and greater functionalities, improvement in WLCSP (Wafer Level Chip Scale Package) technology is necessary to meet the new requirements from today's electronic devices. TSV (Through Silicon Via) technology has always been used as the vertical interconnections for assembly of MEMS-WLCSP packaging. In our development work, we proposed to use an innovative approach to substitute the TSV with TMV (Through Mold Via), using the wafer-level over-molding of vertical Si (silicon) pillars and Cu (copper) wires as vertical interconnections. For the molding process development work, epoxy mold compound (EMC) and silicone mold compound (SMC) materials were studied to explore suitable mold material candidates for good wafer warpage control and void free vertical interconnects structure mold filling. Fine filler (EMC) B and (EMC) C molded to a thin over-mold cap of 150μm gave void free mold fill and the best wafer warpage control for subsequent Cu (cooper) redistributed layers (RDL)s processing. Liquid (EMC) B was observed to be more suitable for encapsulating vertical wires than granular (EMC) C as random wires collapse was observed after the molding process. Greater Cu smearing on the exposed Cu wire interconnections was observed on (EMC) C as compared to (EMC) B after the mold cap was back-grinded to expose the vertical interconnects. Greater Cu smearing could be attributed to the lower modulus for (EMC) C, which resulted in greater galling after back-grinding and greater Cu smearing. In conclusion, the (SMC) candidates have good wafer warpage control, but were not suitable for our MEMS-WLCSP process flow due to void presence in (SMC) D and flattening of wires for (SMC) E. Hence, (EMC) B and (EMC) C were shortlisted for actual wafers molding development.

Today's electronic devices are expected to be fully function, low power consumption and high performance. There are more and more functional modules integrated in a SoC chip. A three-dimension integrated circuit (3-D IC) is developed and in which two or more layers of active electronic components are integrated both vertically into a single circuit. In two-dimension IC, the memory size usually dominated and occupied the most of area. Besides, 3-D IC designs will deal with serious challenges in design space exploration and system validation. In this work, we analyze different system architectures, mainly the architecture of the stacking memory. To demonstrate our 3-D IC design techniques, the stacking memory approach is employed in our “3D-PAC (Parallel Architecture Core)” design. In 3D-PAC, we stack 512KB SRAM directly on top of the logic die which is heterogeneous multi-core computing platform for multimedia application purpose. Finally, we use ESL technology to demonstrate the performance improvement. The result shows that there is 34.89% of speed-up by using the stacking memory architecture.

The need for high power density and high temperature capabilities in today's electronic devices continues to grow. More robust devices with reliable and stable functioning capabilities are needed, for example in aerospace and automotive industries as well as sensor technology. These devices need to perform under extreme temperature conditions, and not show any deterioration in terms of switching speeds, junction temperatures, and power density, and so on. While the bulk of research is performed to source and manufacture these high temperature devices, the device interconnect technology remains under high focus for packaging. The die attach material has to withstand high temperatures generated during device functioning and also cope with external conditions which will directly determine how well the device performs in the field. This literature work seeks to review the numerous research attempts thus far for high temperature die attach materials on wide band gap materials of silicon carbide, gallium nitride and diamond, document their successes, concerns and application possibilities, all of which are essential for high temperature reliability.

Today's electronic devices move drastically towards high speed design feature. The traditional D-flip flop is no longer suitable for designing shift registers because of its low-speed performance. Many different types of shift registers, such as Universal Shift registers, Serial In Serial Out, Serial In Parallel Out, Parallel In Parallel Out and Parallel In Serial Out have been developed. Also, there are many low-power shift register design techniques that have been proposed. However, they are all lagging behind in high speed performances. The shift register design using Single clock pulse with Hold Mode (HM-FF) & without Hold Mode (WHM-FF) Flip Flop can be a potential solution to this problem. The shift register design using this proposed method promises to achieve tremendous improvements in performance of speed. When compared to its conventional counterparts, the proposed design is able to attain more than 41.9% reduction in over all time delay, which is targeted to Xilinx Virtex 6 devices.

Chapter 1 - Voltage References and Voltage Regulators

Call Admission Control (CAC) is recognized as one of the key strategies to achieve satisfactory QoS support for VoIP over IEEE 802.11 WLANs. However, most of the prior CAC solutions for VoIP over WLAN are centralized, and the few distributed CAC schemes proposed so far do not account for issues such as the loss of channel time due to medium contention and the coexistence of VoIP traffic with background traffic such as TCP data flows. In this paper, we describe a distributed CAC scheme which aims at addressing these issues by leveraging on channel monitoring techniques, thus being readily implementable in today's consumer devices. The proposed scheme is thoroughly evaluated by means of testbed experiments as well as network simulations in different scenarios, and it is shown to yield a better CAC performance with respect to prior solutions.

It is well known that most of today's electric and electronic devices frequently work with nonsinusoidal waveforms; then, all the passive R, L, and C components sited in these circuits are involved with nonsinusoidal stimuli. Because of their intrinsic nonlinearity, real resistors, inductors, capacitors, and so on show behaviors that are very different from those expected in a sinusoidal environment. Consequently, a problem of reliable assessment of these components in the presence of nonsinusoidal environments arises. This problem is even more critical in applications such as the creation of hybrid filters, control circuits based on patterns of sensing elements, and circuits of digital protection in power systems, where the design and control of electrical and electronic circuits depend on the correct modeling of the R, L, and C components. In previous research works, the authors proposed a suitable measurement method for the estimation of R, L, and C parameters of passive components in nonsinusoidal conditions. This paper deals with the realization of a measurement instrument, based on a Field Gate Programmable Array, that is able to continuously update the estimated values of the considered components. The instrument realization passes through an optimized implementation of the previously proposed measurement method aimed at minimizing the hardware resources and the computational burden and increasing the measurement rate. After a preliminary tuning of the measurement method, carried out in a simulation environment, the hardware and the software architectures of the realized measurement instrument, together with the measurement strategy, are described and experimentally characterized.

Molecular data storage offers the intriguing possibility of higher theoretical density and longer lifetimes than today's electronic memory devices. Some demonstrations have used deoxyribonucleic acid (DNA), but bottlenecks in nucleic acid synthesis continue to make DNA data storage orders of magnitude more expensive than electronic storage media. Additionally, despite its potential for long-term storage, DNA faces durability challenges from environmental degradation. In this work, we demonstrate nongenomic molecular data storage using molecular libraries redirected from chemical waste streams. This approach requires no synthetic effort and can be implemented by using molecules that have a minimal associated cost. While the technique is agnostic about the exact molecular content of its inputs, we confirmed that some sources contained poly fluoroalkyl substances (PFAS), which persist for long periods in the natural environment and could offer extremely durable information storage as well as environmental benefits. These demonstrations provide a perspective on some of the valuable possibilities for nongenomic molecular information systems.

We present the multiple variable length decode algorithm implemented in most video applications on MDSP. In our implementations we were able to decode multiple symbols per cycle. The implementation is efficient and is targeted towards memory constrained embedded systems. We have confirmed this algorithm in our implementations of H261/3, MPEG2/4 and achieved multifold speedup improvements against algorithms which can decode at the symbol rate only. This limits the decoding throughput capability of these algorithms. Most parallel decoding approaches use the length of the first codeword to detect the second codeword in parallel. By a single table lookup operation we detect multiple codewords without any detection mechanism.

Execution of video algorithms on programmable platforms is limited by the available resources. A novel approach with scalable algorithms and run-time control of output quality and resource usage can transcend such limitations.

Good morning. My name is Tim Heidmann and I'd like to welcome you all to this panel, which is entitled Future Directions in Desktop Video, and I'd especially like to thank all you people who stayed up a little late on Thursday night to come to this panel. It's really good to see you all out there.

We consider the problem of low-rank approximation of massive dense nonnegative tensor data, for example, to discover latent patterns in video and imaging applications. As the size of data sets grows, single workstations are hitting bottlenecks in both computation time and available memory. We propose a distributed-memory parallel computing solution to handle massive data sets, loading the input data across the memories of multiple nodes, and performing efficient and scalable parallel algorithms to compute the low-rank approximation. We present a software package called Parallel Low-rank Approximation with Nonnegativity Constraints, which implements our solution and allows for extension in terms of data (dense or sparse, matrices or tensors of any order), algorithm (e.g., from multiplicative updating techniques to alternating direction method of multipliers), and architecture (we exploit GPUs to accelerate the computation in this work). We describe our parallel distributions and algorithms, which are careful to avoid unnecessary communication and computation, show how to extend the software to include new algorithms and/or constraints, and report efficiency and scalability results for both synthetic and real-world data sets.

Hand-gesture interaction with a smart TV using a conventional camera under restricted ambient illumination is complicated by the varying incident illumination coming from the screen. In this paper, we propose a method for compensating for the poor ambient illumination in the scene captured by a smart TV camera by balancing it against this kind of incident illumination. The proposed framework models the variations in the ambient illumination as a factor of the varying incident illumination caused by the changing multimedia content displayed on the smart TV. Further, by estimating the average incident illumination and measuring its deviation during the scene transition, an illumination intensity correction factor is deduced, and thus ambient illumination is corrected iteratively. To validate the effectiveness of the proposed method, we benchmark it against multiple video sequences depicting the human gesture interaction with a smart device under both low-lighting (typically in the night) and natural-lighting conditions. Furthermore, experiments on such challenging video sequences have demonstrated improved accuracy and robustness of visual target trackers by preprocessing the sequence using our method.