Software-only multiple variable length decoding for real-time video on MDSP

Today's consumer electronic devices feature multiple applications which have to share scarcely available resources. We consider a priority-processing-based video application, which comprises multiple scalable video algorithms (SVAs) that are executed on a shared, virtual platform. This application is given a guaranteed processor share by means of a constant-bandwidth server (CBS), which in addition efficiently reclaims all spare processor time. A decision scheduler distributes the assigned processor share among the SVAs, with the aim to maximize their overall output quality. To correctly distribute this processor share we introduce the concept of a virtual timer. This timer only advances when its associated virtual platform is executing.

High content of reactive oxygen species (ROS) in the human body leads to oxidative stress and serious health problems, such as cancer and cardiovascular or bone diseases. It is also one of the agents that cause collagen damage. Herein, detection of ROS, scavenging of formed carbon-centered radicals and inhibition of collagen fragmentation were performed in a single operation using newly synthesized profluorescent nitroxide PN1via a switch-on approach. Reassembly of acid soluble collagen (ASC) in the presence of hydroxyl and hydroperoxyl radicals, representatives of ROS, was monitored to study the efficiency of the PN1 probe. Self-assembly curves of collagen fibril solution were in accordance with differential scanning calorimetry (DSC) and scanning electron microscopy (SEM) observations, and indicated that PN1 efficiently inhibited the collagen chain scission. In order to prevent the leakage of the probe in materials, a PN2 monomer was successfully incorporated with MMA to form a profluorescent copolymer probe. Furthermore, PN1 and PN2-MMA copolymer probes offered high sensitivity of detection of ROS in the presence of collagen fibrils with detection limits of 1.1 and 2.7 μM, respectively. The mechanism of ROS detection and inhibition of collagen degradation by profluorescent nitroxides was proposed.

The emergence of multi-core and many-core processors has introduced new opportunities and challenges to EDA research and development. While the availability of increasing parallel computing power holds new promise to address many computing challenges in CAD, the leverage of hardware parallelism can only be possible with a new generation of parallel CAD applications. In this paper, we propose a novel multi-algorithm parallel circuit simulation approach (MAPS) and its multi-core implementation to expedite one of the most fundamental CAD applications: transistor-level transient circuit simulation. MAPS starts multiple simulation algorithms in parallel for a given simulation task. By properly synchronizing these algorithms on-the-fly, we exploit the diversity in simulation algorithms to achieve possibly superlinear overall speedup in transient simulation. In addition, our unique multi-algorithm framework allows unique safe exploration of simulation methods that are conventionally discarded due to convergence concerns. As a coarse grained parallel simulation approach, the implementation of MAPS demands a minimum of parallel programming effort and allows for reuse of existing serial simulation codes.

A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder, which is crucial for 5G communication systems. If a traditional reconfigurable cyclic shifter can only shift one input of variable size at a time, a traditional QC-LDPC decoder can only decode one codeword at a time as well. Part of the circuitry of the traditional QC-LDPC decoder inevitably stays in idle during the decoding process if the length (or the lifting parameter) of a codeword is not the maximum, resulting in low hardware efficiency. A segmented reconfigurable cyclic shifter is proposed in this paper, which can be divided into multiple segments of different sizes. Each segment can perform a cyclic shift of an input of different sizes and of different shift values independently. Furthermore, a methodology is proposed to upgrade any state-of-the-art QC-LDPC decoder to a segmented QC-LDPC decoder, by using the proposed segmented shifter. The upgraded segmented QC-LDPC decoder is able to parallelly decode multiple codewords (or inputs) of different lengths at a time. A test chip of the proposed segmented QC-LDPC decoder with the proposed segmented reconfigurable cyclic shifter has been fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology to demonstrate the feature of parallelly decoding multiple codewords. The performance analysis shows that when the number of small codewords is increased from 0 to 100000 per second, the throughput of the traditional QC-LDPC decoder drops from 844.80 Mbps to 4.40 Mbps, while the QC-LDPC decoder with the proposed segmented shifter only slightly drops to 814.01 Mbps. By applying the segmented QC-LDPC decoder in 5G base stations, the base stations are enabled to support more low-traffic users.

One of the challenges in managing cloud computing clusters is assigning resources based on the customers’ needs. For this mechanism to work efficiently, it is imperative that there are sufficient resources reserved to maintain continuous operation, but not too much to avoid overhead costs. Additionally, to avoid the overhead of acquisition time, it is important to reserve resources sufficiently in advance. This paper presents a novel reliable general-purpose mechanism for prediction-based resource usage reservation. The proposed solution should be capable of operating for long periods of time without drift-related problems, and dynamically adapt to changes in system usage. To achieve this, a novel signature-based ensemble prediction method is presented, which utilizes multiple distinct prediction algorithms suited for various use-cases, as well as an anomaly detection mechanism used to improve prediction accuracy. This ensures that the mechanism can operate efficiently in different real-life scenarios. Thanks to a novel signature-based selection algorithm, it is possible to use the best available prediction algorithm for each use-case, even over long periods of time, which would typically lead to drifts. The proposed approach has been evaluated using real-life historical data from various production servers, which include traces from more than 1,500 machines collected over more than a year. Experimental results have demonstrated an increase in prediction accuracy of up to 21.4 percent over the neural network approach. The evaluation of the proposed approach highlights the importance of choosing the appropriate prediction method, especially in diverse scenarios where the load changes frequently.

Phishing remains a significant cybersecurity threat, exploiting individuals and organizations by deceiving them into disclosing sensitive credentials such as usernames, passwords, and financial information. Attackers often use phishing URLs that mimic legitimate websites to lure victims into unknowingly submitting their private data. Given the increasing sophistication of these threats and the lack of cybersecurity awareness among users, it is crucial to develop robust detection mechanisms. This research introduces an ensemble machine learning model for phishing intrusion detection and URL classification, leveraging multiple classification algorithms to enhance accuracy and reliability. The proposed model analyzes key URL-based features to differentiate between legitimate and phishing URLs, providing an adaptive and intelligent detection system. By integrating multiple machine learning techniques, the ensemble approach improves detection rates while reducing false positives, ensuring a more effective defense against evolving phishing threats. The study aims to develop a client-side phishing detection tool that empowers internet users with realtime protection and assists cybersecurity professionals in identifying phishing patterns. The findings of this research contribute to advancing security measures for online users, mitigating the risks associated with phishing attacks, and fostering a safer digital ecosystem

Reducing the number of single operation during matrix-vector multiplication is a method of accelerating of multiplication and decreasing power consumption. It is often not a simple task. The paper presents the methods for looking for the proper structure of the matrix using an evolutionary algorithm and the hill-climbing. The evaluation function, defined in the paper, leads to improvements in the form of the matrix by getting a proper structure. The optimisation process is made by using a special defined crossover and two types of mutations. The investigation presented in the paper confirms the possibility of automatically finding a special structure of a matrix.

This paper gives a description of our real-time software MPEG-4 video decoder. The performance of the decoder and the fast algorithms used for real-time decoding are discussed. Our techniques used to speed up four computationally intensive modules, inverse discrete cosine transform, context-based arithmetic decoding, padding, and variable length decoding, are also presented in this paper. Our decoding speed is improved so that software real-time video decoding is possible.

A coarse-grained reconfigurable processor tailored for accelerating multiple bioinformatics algorithms is proposed. In this paper, a programmable and scalable architectural platform instantiates an array of coarse grained light weight processing elements, which allows arbitrary partitioning, scheduling schemes and capable of solving complete four popular bioinformatics algorithms: the Needleman-Wunsch, Smith-Waterman, and HMMER on sequencing, and Maximum Likelihood on phylogenetic. The key difference of the proposed CGRA based solution compared to FPGA and GPU based solutions is a much better match on architecture and algorithms for the core computational needs, as well as the system level architectural needs. For the same degree of parallelism, we provide a 5X to 14X speed-up improvements compared to FPGA solutions and 15X to 78X compared to GPU acceleration on 3 sequencing algorithms. We also provide 2.8X speed-up compared to FPGA with the same amount of core logic and 70X compared to GPU with the same silicon area for Maximum Likelihood.

Turbo equalization has been shown to have excellent performance for magnetic recording channels, and permits operation at low signal-to-noise ratios. Soft-output algorithms, such as the BCJR or SOVA algorithms, are used as the detector in proposals for turbo equalization. However, these algorithms are difficult to implement effectively at the bit rates and power consumption levels required for hard drives. The paper considered an implementation of the BCJR algorithm where the state metrics are vector quantized, and the operations are performed using table lookups. Table lookup operations are efficiently implemented in both hardware and software. The proposed algorithm uses off-line computation to generate vector quantizers and lookup tables, and the only run-time operations are table lookups. Using vector quantization, the size of the lookup tables can be of reasonable size. Further, the compressed representation reduces the required state metric storage.

The Shot Boundary Detection (SBD) is an early step for most of the video applications involving understanding, indexing, characterization, or categorization of video. The SBD is temporal video segmentation and it has been an active topic of research in the area of content based video analysis. The research efforts have resulted in a variety of algorithms. The major methods that have been used for shot boundary detection include pixel intensity based, histogram-based, edge-based, and motion vectors based, technique. Recently researchers have attempted use of graph theory based methods for shot boundary detection. The proposed algorithm is one such graph based model and employs graph partition mechanism for detection of shot boundaries. Graph partition model is one of the graph theoretic segmentation algorithms, which offers data clustering by using a graph model. Pair-wise similarities between all data objects are used to construct a weighted graph represented as an adjacency matrix (weighted similarity matrix) that contains all necessary information for clustering. Representing the data set in the form of an edge-weighted graph converts the data clustering problem into a graph partitioning problem. The algorithm is experimented on sports and movie videos and the results indicate the promising performance.

This research focuses on enhancing the detection mechanisms for Distributed Denial of Service (DDoS) attacks using advanced machine learning techniques. We explore two innovative approaches: a metaclassifier stacking model and a transfer learning model, utilizing the CICDDoS2019 and CICIDS2017 datasets for training and evaluation. The first approach integrates K-Nearest Neighbors (KNN), Support Vector Machine (SVM), and Random Forest (RF) algorithms through a logistic regression metaclassifier. This ensemble method harnesses the strengths of each algorithm, leading to improved metrics such as accuracy, precision, recall, and F1-score. The second approach employs transfer learning, where a pre-trained Artificial Neural Network (ANN) on the CICIDS2017 dataset is fine-tuned with the CICDDoS2019 dataset. This technique demonstrates the benefits of knowledge transfer, achieving high detection performance with reduced training time. Our findings reveal that both methods significantly enhance DDoS detection. The metaclassifier approach delivers superior performance metrics but requires more computational resources. In contrast, the transfer learning approach provides an efficient balance between performance and computational demand, ideal for rapid deployment scenarios. In summary, this study highlights the efficacy of combining multiple algorithms and leveraging pre-trained models to improve DDoS detection accuracy and efficiency. These approaches offer promising directions for developing robust and effective DDoS detection systems.

System-level designers typically rely on white-box detailed descriptions of embedded systems in order to perform their design choices and optimisations. The white-box approach assumes that the complexity of the system can be managed by decomposing the global system into a set of simple and well-described components. This assumption is generally not true when non-linear interactions happen between the different subsystems. This paper explores, as an alternative, a black-box modelling methodology based on intelligent data analysis in order to support system-level designers in characterising the performance of embedded applications. The rationale behind this approach is that nowadays the designer can easily store large amount of data related to the system, and consequently discover relevant information by analysing them in a black-box fashion. As a case study, we address the performance modelling of software applications running on an embedded microprocessor. We introduce a data analysis method which, on the basis of a high-level characterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on a embedded processor. We propose the adoption of a local learning technique (lazy learning), which proved already to be effective in previous works, to model the unknown input/output relation between the hardware/software parameters of the application and the number of execution cycles. Experiments with standard computational code (sorting, mathematical computation) and with a specific streaming algorithm for MPEG variable length decoding are presented to support this claim.

An improved implementation scheme for AVS entropy decoding based on FPGA is proposed in this paper. The additional control circuit is used to get rid of the code streams parsed every cycle without adding any parsing periods. And it makes the barrel shifter prepositive so as to balance the time sequence path in the front end. In this way, the deficiency in the traditional structure of variable length decoding is conquered. Compared with the traditional structure, the proposed scheme achieves 43.2 percent time sequence improvement at the cost of 2.5 percent LE and the real-time high-definition (4:2:2) video decoding sequence can be implemented on Cyclone II EP2C35F672C6.

This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the performance modelling of software applications running on an embedded microprocessor. We propose a data analysis method, which, on the basis of a parameterisation of the software functionality and the hardware architecture, is able to predict the number of execution cycles on an embedded processor. Experiments with standard computational code (sorting, mathematical computation) and with MPEG variable length decoding are presented to support this claim.