Constructive multi-phase test point insertion for scan-based BIST

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

We propose timing-driven test point insertion methods for a full-scan based BIST scheme and for a partial-scan based BIST scheme, where the global flip-flop cycles have been broken by the scan flip-flops. The objective is to minimize the performance as well as the area impact due to the insertion of test points while achieving a high fault coverage under the pseudo-random BIST scheme. The gradient-based method is used and extended to estimate the random-pattern testability improvement factors for the test point candidates of either full-scan based or partial-scan based BIST. We also propose a symbolic computation technique to compute testability for circuits under the partial-scan based BIST scheme. Experimental results show that the performance degradation of test point insertion could be unacceptably high if the cost function used for test point selection does not include the performance penalty. Using our timing-driven algorithm, zero performance degradation and a high fault coverage can always be achieved using a small number of test points.

A method of data collecting, training, and using artificial neural networks (ANNs) for evaluating test point (TP) quality for TP insertion (TPI) is presented in this study. The TPI method analyzes a digital circuit and determines where to insert TPs to improve fault coverage under pseudo-random stimulus, but in contrast to conventional TPI algorithms using heuristically-calculated testability measures, the proposed method uses an ANN trained through fault simulation to evaluate a TP's quality. The time of feature extraction is demonstrated to be significantly faster compared to heuristic-based TP evaluation, and the impact of inserted TPs is shown to provide superior stuck-at fault coverage compared to conventional heuristic-based testability analysis.

Test point insertion methods to reduce the number of test patterns at register transfer level are required for the adaptability of traditional VLSI design flows and the reduction of time to search test point locations. In this paper, we propose a design-for-testability method at register transfer level to enable operational units as many as possible to be concurrently tested in scan testing. Using test point insertion and controller augmentation, the proposed design-for-testability method allocates input test registers and an output test register to inputs and an output of each operational unit in a data-path, respectively. Test compaction efficiency becomes high by enabling effective concurrent testing for operational units. Experimental results on high-level benchmark circuits show that our proposed method reduced the number of test patterns by 20% with 6.5 % area overhead on average.

A low-overhead scheme for achieving complete (100%) fault coverage during built-in self test of circuits with scan is presented. It does not require modifying the function logic and does not degrade system performance (beyond using scan). Deterministic test cubes that detect the random-pattern-resistant (r.p.r.) faults are embedded in a pseudorandom sequence of bits generated by a linear feedback shift register (LFSR). This is accomplished by altering the pseudorandom sequence by adding logic at the LFSR's serial output to fix certain bits. A procedure for synthesizing the bit-fixing logic for embedding the test cubes is described. Experimental results indicate that complete fault coverage can be obtained with low hardware overhead. Further reduction in overhead is possible by using a special correlating automatic test pattern generation procedure that is described for finding test cubes for the r.p.r. faults in a way that maximizes bitwise correlation.

There is mounting evidence that automatic test pattern generation tools capable of producing tests with high coverage of defects occurring in the large semiconductor nanometer designs unprecedentedly inflate test sets and test application times. A design-for-test technique presented in this paper aims at reducing deterministic pattern counts and test data volume through the insertion of conflict-aware test points. This methodology identifies and resolves conflicts across internal signals allowing test generation to increase the number of faults targeted by a single pattern. This is complemented by a method to minimize silicon area needed to implement conflict-aware test points. The proposed approach takes advantage of the conflict analysis and reuses functional flip-flops as drivers of control points. Experimental results on industrial designs with on-chip test compression demonstrate that the proposed test points are effective in achieving, on average, an additional factor of $2\times $ – $4\times $ compression for stuck-at and transition patterns over the best up-to-date results provided by the embedded deterministic test (EDT)-based regular compression.

TPI (test point insertion) can be used to improve the pseudo-random testability of circuits. However, many TPI algorithms are based on COP, which can only cope with Boolean circuits, while in the industry three-state circuits are also found. In this paper the testability analysis method COP, and the COP based HCRF TPI algorithm, are extended with three-state capabilities, and the HCRF TPI algorithm is adjusted in such a way that better PR (pattern resistant) fault coverage improvements can be achieved for Boolean as well as for three-state circuits.

Functional test sequences were shown to detect unique defects in VLSI circuits. This is thought to be due to the fact that they are applied at-speed. However, functional test sequences do not achieve complete stuck-at fault coverage. Therefore, scan-based stuck-at tests, as well as other types of tests, are typically also applied. This increases the amount of test resources required for test application. We describe a procedure for inserting (limited) scan operations into a functional sequence in order to improve its stuck-at fault coverage, thus reducing or eliminating the need for separate scan-based stuck-at tests. Between scan operations, the functional test sequence can still be applied at-speed; however, a higher stuck-at fault coverage is achieved.

A challenging issue is the derivation of a finite test suite from a given LOTOS specification modeled by a labeled transition system (LTS) such that complete fault coverage is guaranteed for a certain class of implementations with respect to a particular conformance relation. It is shown in this paper that this problem can be solved by translating an LTS into an input/output finite state machine (FSM) for trace or failure semantics, respectively, and subsequently applying existing FSM-based methods for test derivation with complete fault coverage. It is also demonstrated that the obtained tests can be further optimized taking into account the specifics of the FSMs constructed from the LTSs.KeywordsTest SuiteFinite State MachineLabel Transition SystemConformance TestingImplementation Under TestThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

A stereo-photogrammetric method for three-dimensional reconstruction of points in low-dose digital X-ray images obtained using a scanner with similar imaging geometry to that of computed tomography scan projection radiography, was analysed. A calibration frame containing 25 radio-opaque markers with known three-dimensional locations was scanned, and the accuracy of reconstruction of the marker positions under varying control point configurations and separation angles was assessed. Errors of less than 1 mm were obtained when nine test points were reconstructed, with 16, 11 and 7 control points at a 90 degrees separation angle, and with 16 and 11 control points at 75 degrees and 60 degrees separation angles. The optimum reconstruction, with a resultant error of 0.68 mm, was found to occur at a separation angle of 90 degrees, with the largest number of control points (16) used to calculate the parameters of the transformation. Extrapolation in the scanning direction beyond the space defined by the control points gave errors of less than 2 mm. This method should be suitable for three-dimensional point reconstruction in applications such as cephalometry, brachytherapy planning and assessment of spinal shape.

Test cost is increasingly becoming a major component of a product's design cost in scaled technologies. Exponential increase in test data volumes for sub-45 designs, especially for testing delay faults has led to large increase in ATE cost and test application time. In order to reduce external test cost, Logic BIST has been explored as a possible alternative to manufacturing test [1-5]. However, this paper shows that a large number of faults in BIST logic of large IWLS'05 and ITC'99 benchmark processors remain undetected after BIST run (42% of stuck-at and 34% of transition faults on average) and thus, BIST logic needs to be tested properly. This paper proposes a hierarchical BIST methodology `HBIST' which uses different BIST techniques to obtain complete stuck-at and transition fault coverage of CUT and then introduces additional levels of BIST logic to test for faults in the BIST logic at the preceding levels. A design methodology is proposed to optimize the number of additional levels of BIST required while keeping the BIST area and power overhead, and the addition of extra faults in BIST logic minimal. Experiments on large benchmarks show an average of 95.9% CUT stuck-at fault coverage (ATPG coverage of 96.4%) and 93.5% CUT transition fault coverage (ATPG coverage of 95.3%) is obtained using HBIST. Also, up to 99.2% (average 93.2%) reduction in external ATE test cost (including cost needed to test additional BIST levels) is obtained using two levels of BIST at 7% average area overhead (compared to scan overhead of 38.2%) and 18% increase in test power.

Area-efficient high-coverage LBIST

Integrated circuits used in critical and high reliability applications have often strict test requirements including high test coverage and limited test time. Achieving a high test coverage using built-in self-test (BIST) has proven difficult. Methods such as test point insertion or deterministic BIST can provide high test coverage but introduce significant area overhead and design effort. In this paper, we propose a computational algorithm that uses a linear XOR model of the logic BIST (LBIST) structure and fault partitioning to extract seeds for partial ATPG patterns. Partial ATPG patterns are used to decrease the complexity of the algorithm when solving linear XOR equations to generate deterministic seeds. The extracted seeds are stored in a nonvolatile memory on- or off-chip. Results show that for most designs, patterns generated from the extracted ATPG seeds are significantly more effective in detecting faults and can achieve higher test coverage than LBIST.

Conventional automatic test pattern generation (ATPG) algorithms fail when applied to asynchronous NULL convention logic (NCL) circuits due to the absence of a global clock and presence of more state-holding elements, leading to poor fault coverage. This paper presents a design-for-test (DFT) approach aimed at making asynchronous NCL designs testable using conventional ATPG programs. We propose an automatic DFT insertion flow (ADIF) methodology that performs scan and test point insertion on NCL designs to improve test coverage, using a custom ATPG library. Experimental results show significant increase in fault coverage for NCL cyclic and acyclic pipelined designs.

The proposed work has a test pattern generator for built-in self-test (BIST) based applications along with test data compression. Test patterns are produced with desired levels of toggling and improved fault coverage is obtained when compared with BIST-based pseudorandom pattern generators (PRPG). The pattern generator comprises of a pseudorandom pattern generation unit, a toggle generation and control unit, a hold register unit. Preselected toggling (PRESTO) generator allows user defined levels of toggling. The pattern generator is a linear finite state machine which drives a phase shifter, which reduces correlation of patterns. This paper proposes a test compression method which elevates the compression efficiency that has not been obtained by conventional compression techniques. It does not need any core logic modifications like test point insertion and thus the compression technique is nonintrusive. This hybrid technique of BIST along with test compression achieves fault coverage above 90%. Experimental results are obtained for ISCAS 85, ISCAS 89 and ITC 99 standard benchmark circuits. The PRESTO generator can effectively function as a decompressor also and hence area is reduced.