Continuous error detection (CED) for reliable communication

Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new continuous error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection, first introduced by Bell, Witten, and Cleary (1990), is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error.

Error control coding improves reliability and efficiency of wireless communication systems. This research delves into the latest advancements in error control coding schemes for wireless communication systems, with a specific focus on their application within the domain of Low Power Wide Area Networks (LPWANs) such as Narrowband Internet of Things (NB-IoT) systems, LoRa energy-efficient hardware design, random access control systems, and wireless sensor networks. In the context of LPWANs, particularly NB-IoT systems, we investigate the adaptive coding and modulation (ACM) in NB-IoT systems, which adapts coding rates and modulation techniques to changing channel circumstances. Comprehensive analysis of the literature review shows that the proposed approaches are more energy efficient and less error-prone than fixed coding and modulation schemes. Using Cell Design Methodology (CDM), Single Error Correction (SEC) codes are optimized for energy efficiency. Power and energy efficiency have improved in standard CMOS and CDM logic systems. This impacts IoT devices, memory storage, and security systems. Next, Forward Error Correction (FEC) is examined for ALOHA-based random-access control systems wherein packet loss rate and spectral efficiency metrics are mathematically calculated. FEC is beneficial, especially when time and frequency synchronization diverge. Monte Carlo simulations studied in the literature shows that FEC improves satellite communication systems. This review establishes benefits of FEC, notably in satellite communications systems. In addition, Wireless Sensor Networks (WSNs) error control techniques and network reliability and performance are examined along with Convolutional, Turbo, Low density parity check codes(LDPC), and Polar error correction coding (ECC) methods. We learn about their benefits, drawbacks, and implementation challenges by assessing their efficacy, efficiency, and applicability in wireless sensor networks (WSN) applications. This study further highlights advancements of energy-efficient error control coding when, integrated into network designs alongwith the trade-offs between efficacy and intricacy to help improve wireless communication networks. Finally, this study summarizes current error control coding approaches for wireless communication systems. We provide insights into improving reliability, energy conservation, and efficacy by examining ACM, CDM, FEC, and error correction coding (ECC) across varied domains including LPWAN and IoT technologies with earnest hope to facilitate researchers, engineers, and professionals working in the field of error control coding in wireless communication.

Error correction coding, channel coding, also known as error control coding, is to add some redundant code elements, or check code elements, to form a correlated sequence of code elements—code words and to use the correlation property between code elements to detect and correct errors when decoding. Different error correction coding schemes have different error detection and correction capabilities. This paper designs a combination of parity check and cyclic redundancy check (CRC) to improve the error detection and correction capabilities with minimum cost, so that the system can transmit information more efficiently while also having high transmission reliability.

In computer communication and telecommunication applications, error detection and correction techniques must be employed to ensure a reliable data transmission from the source to the destination. Two of the most prevailing techniques, Cyclic Redundancy Check (CRC) detection and Hamming code correction, are implemented and analyzed. The CRC method picks up prominence because it joins three focal points: extraordinary blunder identification capacities, minimal overhead, and simplicity of usage. Moreover, both the CRC and Hamming code are binary linear codes. However, one significant difference is that Hamming code only works on data of some fixed size (depending on the Hamming code used), whereas CRC is a convolution code that works on data of any size. In this paper, the authors will show how CRC helps in removing errors by passing three distorted signals and using CRC to receive the signal error free in the MATLAB environment.

Error detection and correction options for data services in B-ISDN (broadband integrated services digital network) are examined. B-ISDN uses the asynchronous transfer mode (ATM) technique for transporting voice, data, and video services. Currently, the ATM cell header size, functions, and adaption layer fields for data services are being standardized in CCITT. Error protection for data payloads will be provided by a per-cell CRC (cyclic redundancy check) field. Different data services may need different degrees of error protection. The authors discuss and analyze different options for error detection and correction by considering various schemes ranging from no error protection to only error detection. Based on the analysis and results presented, a per-cell CRC has been adopted in the adaptation layer for all data services. The per-cell CRC substantially improves cell misdelivery for all data services. For error-insensitive data services, single-bit correction over MID and segment-type fields improves cell loss substantially. At the same time, single-bit correction keeps cell misdelivery sufficiently low (1 in 10/sup 13/ in the worst case). >

There is an increasing need for high-capacity, highdensity storage media that can retain data for a long time, due to the exponential development in the capacity of information generated. The durability and high information density of synthetic deoxyribonucleic acid (DNA) make it an attractive and promising medium for data storage. DNA data storage technology is expected to revolutionize data storage in the coming years, replacing various Big Data storage technologies. As a medium that addresses the need for high-latency, immutable information storage, DNA has several potential advantages. One of the key advantages of DNA storage is its extraordinary density. Theoretically, a gram of DNA can encode 455 exabytes, or 2 bits per nucleotide. Unlike other digital storage media, synthetic DNA enables large quantities of data to be stored in a biological medium. This reduces the need for traditional storage media such as hard disks, which consume energy and require materials such as plastic or metals, and also often leads to the generation of electronic waste when they become obsolete or damaged. Additionally, although DNA degrades over thousands of years under non-ideal conditions, it is generally readable. Furthermore, as DNA possesses natural reading and writing enzymes as part of its biological functions, it is expected to remain the standard for data retrieval in the foreseeable future. However, the high error rate poses a significant challenge for DNA-based information coding strategies. Currently, it is impossible to execute DNA strand synthesis, amplification, or sequencing errors-free. In order to utilize synthetic DNA as a storage medium for digital data, specialized systems and solutions for direct error detection and correction must be implemented. The goal of this paper is to introduce DNA storage technology, outline the benefits and added value of this approach, and present an experiment comparing the effectiveness of two error detection and correction codes (Hamming and CRC) used in the DNA data storage strategy.

High frame-corruption is widely observed in Long Range Wide Area Networks (LoRaWAN) due to the coexistence with other networks in ISM bands and an Aloha-like MAC layer. LoRa's Forward Error Correction (FEC) mechanism is often insufficient to retrieve corrupted data. In fact, real-life measurements show that at least one-fourth of received transmissions are corrupted. When more frames are dropped, LoRa nodes usually switch over to higher spreading factors (SF), thus increasing transmission times and increasing the required energy. This paper introduces ReDCoS, a novel coding technique at the application layer that improves recovery of corrupted LoRa frames, thus reducing the overall transmission time and energy invested by LoRa nodes by several-fold. ReDCoS utilizes lightweight coding techniques to pre-encode the transmitted data. Therefore, the inbuilt Cyclic Redundancy Check (CRC) that follows is computed based on an already encoded data. At the receiver, we use both the CRC and the coded data to recover data from a corrupted frame beyond the built-in Error Correcting Code (ECC). We compare the performance of ReDCoS to (i) the standard FEC of vanilla-LoRaWAN, and to (ii) Reed Solomon (RS) coding applied as ECC to the data of LoRaWAN. The results indicated a 54x and 13.5x improvement of decoding ratio, respectively, when 20 data symbols were sent. Furthermore, we evaluated ReDCoS on-field using LoRa SX1261 transceivers showing that it outperformed RS-coding by factor of at least 2x (and up to 6x) in terms of the decoding ratio while consuming 38.5% less energy per correctly received transmission.

6 - Applications to Communication Systems

Orthogonal frequency division multiplexing (OFDM)-based wireless transmission technologies such as WiMAX are now widely deployed, and the frame check sequence (FCS) scheme is used to enhance the reliability of OFDM-based systems. As the padding overhead cannot be completely avoided in such systems when variable-length medium access control (MAC) frames are encapsulated, the authors propose a novel cyclic redundancy check (CRC)-based error-correction scheme that utilises the frame padding overhead to carry as much extra segmented FCS information as possible. In a multi-hop relay environment, a mobile station might receive a multicast frame more than once, so the error bit correction scheme could be triggered in the first transmission. In the IEEE's work, the original CRC scheme is optional and only has limited error-detection capability in upper MAC layer. FCS requires a few bits in a frame, but in our work, CRC is compulsory and all sub-FCSs are carried by padding space without using any extra bit. For the best error-correction capability, all transmissions must be padded as many sub-FCSs are possible in cross layer. The proposed approach achieves a significant performance improvement over the legacy FCS scheme in terms of error detection and correction of multicast frames in a transparent mode multi-hop relay network, and it is redundancy-free as well as energy efficient. The authors assess the performance improvement via both mathematical analysis and simulations. The results show that the mobile stations get significant improvement of goodput and utilisation in an error-prone WiMAX multi-hop relay network.

Cyclic Redundancy Check (CRC) is a widely used error detection code in digital communication systems to detect errors in data transmitted between transmitter and receiver. With the development of Internet-of-Things (IoT) technology, where many devices communicate wirelessly, the application of error detection codes such as CRC is essential to obtain reliable communication. The computation of CRC can be implemented in hardware using a linear feedback shift register (LFSR) or in software with shift and bitwise exclusive OR (XOR) operations for polynomial division. Due to the frequent use of CRC in wireless communication for IoT, research for the design and implementation of CRC continues to this day. This study aims to design and implement the encoder and decoder of CRC-8 with generator polynomial 0x07 on IoT devices. Two algorithms for computing the CRC, namely bitwise computation using LFSR and another one using lookup tables, are implemented on the Arduino Uno R3 board. Two Arduino boards connected in serial were used to verify the encoder and decoder implementation in the data transmission and error detection process. The experiment results showed that the encoder could correctly calculate the CRC value from the input data. Furthermore, the computation using lookup tables takes about four times faster than the bitwise method but requires more memory. In contrast, the bitwise computation method requires less memory but slower computation time. When testing using input data of 128 characters, the bitwise-based encoder requires a computation time of 2.37 milliseconds, while the lookup table-based encoder utilizing a lookup table requires a computation time of 0.5 milliseconds. In the error detection test, the results demonstrated that the receiver could detect errors in the transmitted data with a percentage of 100%.

Cyclic redundancy check (CRC) bits that are conventionally used for error detection have recently found a new application in universal mobile telecommunications system standard for message length detection of variable-length message communications. It was anticipated that the CRC bits, when they are coworked with the inner convolutional code, can be used to detect the receiver-unaware of the message length-without much degradation in their error detection capability. This is unfortunately not true when the offset or difference between the wrong detected length and the true length is small. Two improvements, i.e., the DoCoMo's reverse CRC method and the flip CRC method, were accordingly proposed. In this paper, we revisited the flip CRC modification by considering the impact of joint decoding of the CRC code and the convolutional code. By generalizing the condition for the selection of the flip polynomials, we found that under error-free transmission, the range of the length offsets, at which the false length probability conditioning on the true message length can be made exactly zero (and hence, is minimized), can be extended from to , where and are, respectively, the number of the CRC bits and the memory order of the convolutional code. In addition, an upper bound and a lower bound for the overall false length probability with respect to a uniform pick of the true message length over a candidate message length set are derived. It is then confirmed numerically that the two bounds almost coincide for moderate value. Simulations show that the false length probability obtained analytically under error-free transmission assumption only mildly degrades for moderate-to-high SNRs. Interestingly, we also found that the system block error rate of the flip CRC method can be well approximated by the performance curve of the adopted convolutional code up to a certain SNR, and approach an error floor determined well by the previously derived false length probability bounds beyond this SNR, thereby facilitating the selection of the system parameters, such as the number of CRC bits and the memory order of the convolutional code.

Error-correcting codes (ECC) are widely used during data transfer in wireless communication systems as well as in computer memory architectures. The error-correcting process is based on sending data with extra parity bits and decoding the received data for error correction. The first error detection and correction code, introduced in 1950, Hamming Code (7,4) is a linear error-correcting code able to detect and correct a single-bit error by encoding 7-bit data from 4-bit data, including 3 parity bits. Previous efforts using unipolar resistive random access memory (ReRAM) based in-memory computation of Hamming Code (7,4) resulted in 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> times lower power consumption compared to GPU and 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> times less than CPU-based computations. However further reduction of power consumption can be achieved by vector-matrix multiplication (VMM) using bipolar ReRAM arrays. In the VMM based approach, an encoding or decoding code matrix is stored in the array where it leverages the nonvolatile properties of ReRAM. With the VMM approach, the total number of computation cycles is not limited by the endurance of the ReRAM devices. Here we report the first experimental results of encoding and decoding Hamming code (7,4) using 1 transistor 1 hafnium oxide-based ReRAM (1T1R) arrays fabricated using 65nm CMOS technology. Our results show bipolar 1T1R arrays can correctly encode 4-bit message data to 7 bit encoded data as well as error position detection with overall 3 fold less power consumption than previously reported unipolar ReRAM crossbar array-based computation. Furthermore, we propose and simulate a peripheral circuit to convert the analog column output from a 1T1R array to single-bit binary output using the Cadence Spectre simulator. Our results pave the way for using a memristor-based fast and scalable hardware solution for encoding decoding of error-correcting codes

The authors investigate error detection and correction options for data services in the broadband integrated services digital network (B-ISDN). They discuss and analyze different options for error detection and correction by considering the various alternatives ranging from no error protection to only error detection. Based on the analysis and results presented, a per-cell cyclic redundancy check (CRC) has been adopted in the adaptation layer for all data services. The authors focus on the ATM (asynchronous transfer mode) adaptation layer (AAL) error protection alternatives available within the framework of a per-cell CRC. The ATM cell header and AAL fields are described. A 4 bit cell sequence number for detecting cell misordering is analyzed. Based on the analysis, it is concluded that the 4 bit sequence number provides a powerful capability for detection of cell misordering.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Error Control CodesComputing has always had to live with errors, especially in data transmission and data recording.Sometimes these errors are only a nuisance and a simple retry can obtain satisfactory, accurate, data.But sometimes an error can be serious, and perhaps even disastrous if an accurate original copy is inaccessible.Two related, but somewhat parallel disciplines, have developed to deal with the handling of erroneous data, both part of the general theme of "Coding Theory" and collected under the generic title of "Error Control".Error Detection Error Detection extends the ideas of parity to provide powerful and reliable detection of errors, usually by appending a "checksum" of 8, 16 or 32 bits to the data.The checksum is carefully designed to be sensitive to the probable errors: a checksum for manual data entry must be sensitive to digit transposition and repetition, while one for data transmission must detect long bursts of errors.A detected error invariably leads to an alarm of some sort and request for data re-entry or retransmission.

During data exchange in wireless networks, an error in transmission can occur. Corrupted data cannot be further processed without a correction. A technique based on either Automatic Repeat reQuest (ARQ) or Forward Error Correction (FEC) is conventionally used to repair erroneous data in wireless networks. The ARQ is backward mechanism that uses a feedback channel for the confirmation of error-free data delivery or to request a retransmission of corrupted data. This method can increase a network throughput if radio channel conditions are getting worse (Sambale et al., 2008). On the other hand, the ARQ method increases the delay of packets due to the retransmission of former unsuccessfully received packets. The FEC can increase user’s data throughput over the channel with poor quality despite the fact that additional redundant bits are coded together with users’ data at the transmitter side. The method combining both above mentioned methods is called Hybrid ARQ (HARQ). All three error correction mechanisms are implemented on physical and/or Medium Access Control (MAC) layer.