Perancangan dan Implementasi Encoder dan Decoder CRC-8 untuk Pendeteksian Error pada Transmisi Data antar Perangkat IoT

A cyclic redundancy check (CRC) is one of the most commonly used error detecting codes in communication and storage devices. Before a message is transferred, a transmitter calculates the CRC using the agreed upon polynomial called a generator, and attaches the resulting residue to the message. When the message is received, a receiver calculates the CRC using the same polynomial and verifies the message. If the two CRC values are different, it means an error has occurred during the data transfer. A CRC is easy to implement in hardware using linear feedback shift registers or in software using a simple polynomial evaluation, or a table lookup for a faster speed. In this paper, a fast CRC computation is presented using a software based parallelization scheme. In an ARM Cortex-A15 implementation of the proposed methodology, it achieves 2.6 times faster speed compared to a conventional table lookup CRC computation.

Cyclic Redundancy Check (CRC) leverages to detect the error of digital data throughout generation, transmission, storage or processing. CRCs are widely used for being simple to execute in binary appliances, crafty to mathematical simulation as well as exclusively performance oriented at identifying generic deviation occured due to intrusion in communication channels. Commonly, hardware implementation of Cyclic Redundancy Check (CRC) computations rely on the Linear Feedback Shift Registers (LFSRs). LFSR framework processes bits serially that is one message bit per clock cycle but while considering high-speed data communications, serial implementation speed is significantly inadequate which causes delay. In this research, a hardware architecture is proposed for parallel computation. Its architecture is not polynomial dependent. After testing its functionality using ModelSim, it is implemented in Altera DE1 FPGA (Field Programmable Gate Array) board and analyzed using Quartus II, TimeQuest Timing Analyzer and Power Play Power Analyzer tools. It is found that the designed took 2771 LEs (Logical Elements), it has 102 pins and consumed 120.68 mW power. Functionality test and FPGA implementation showed that CRC was computed in single clock pulse of frequency of 23.71 MHz and its throughput is 1.656 Gbps. It can be configured for a different polynomial at any time externally. The focus of the research is to represent an efficient, better throughput along with compact systematic interpretation for parallel CRC hardware which will alleviate the flaws including the challenges of the existing CRC checker which will be prominent for next generation high speed communication.

There is an increasing need for high-capacity, highdensity storage media that can retain data for a long time, due to the exponential development in the capacity of information generated. The durability and high information density of synthetic deoxyribonucleic acid (DNA) make it an attractive and promising medium for data storage. DNA data storage technology is expected to revolutionize data storage in the coming years, replacing various Big Data storage technologies. As a medium that addresses the need for high-latency, immutable information storage, DNA has several potential advantages. One of the key advantages of DNA storage is its extraordinary density. Theoretically, a gram of DNA can encode 455 exabytes, or 2 bits per nucleotide. Unlike other digital storage media, synthetic DNA enables large quantities of data to be stored in a biological medium. This reduces the need for traditional storage media such as hard disks, which consume energy and require materials such as plastic or metals, and also often leads to the generation of electronic waste when they become obsolete or damaged. Additionally, although DNA degrades over thousands of years under non-ideal conditions, it is generally readable. Furthermore, as DNA possesses natural reading and writing enzymes as part of its biological functions, it is expected to remain the standard for data retrieval in the foreseeable future. However, the high error rate poses a significant challenge for DNA-based information coding strategies. Currently, it is impossible to execute DNA strand synthesis, amplification, or sequencing errors-free. In order to utilize synthetic DNA as a storage medium for digital data, specialized systems and solutions for direct error detection and correction must be implemented. The goal of this paper is to introduce DNA storage technology, outline the benefits and added value of this approach, and present an experiment comparing the effectiveness of two error detection and correction codes (Hamming and CRC) used in the DNA data storage strategy.

In computer communication and telecommunication applications, error detection and correction techniques must be employed to ensure a reliable data transmission from the source to the destination. Two of the most prevailing techniques, Cyclic Redundancy Check (CRC) detection and Hamming code correction, are implemented and analyzed. The CRC method picks up prominence because it joins three focal points: extraordinary blunder identification capacities, minimal overhead, and simplicity of usage. Moreover, both the CRC and Hamming code are binary linear codes. However, one significant difference is that Hamming code only works on data of some fixed size (depending on the Hamming code used), whereas CRC is a convolution code that works on data of any size. In this paper, the authors will show how CRC helps in removing errors by passing three distorted signals and using CRC to receive the signal error free in the MATLAB environment.

Linear feedback shift register (LFSR) is an important component of the cyclic redundancy check (CRC) operations and BCH encoders. The contribution of this paper is two fold. First, this paper presents a mathematical proof of existence of a linear transformation to transform LFSR circuits into equivalent state space formulations. This transformation achieves a full speed-up compared to the serial architecture at the cost of an increase in hardware overhead. This method applies to all generator polynomials used in CRC operations and BCH encoders. Second, a new formulation is proposed to modify the LFSR into the form of an infinite impulse response (IIR) filter. We propose a novel high speed parallel LFSR architecture based on parallel IIR filter design, pipelining and retiming algorithms. The advantage of the proposed approach over the previous architectures is that it has both feedforward and feedback paths. We further propose to apply combined parallel and pipelining techniques to eliminate the fanout effect in long generator polynomials. The proposed scheme can be applied to any generator polynomial, i.e., any LFSR in general. The proposed parallel architecture achieves better area-time product compared to the previous designs.

The GDDR5 provides cyclic redundancy check (CRC) function to ensure a high speed operation. The GDDR5 calculates the CRC with read data and transmits the results on error detection code (EDC) pins. This paper presents a scheme to reduce calculation time of CRC when the read data bus inversion (DBI) is enabled. This scheme is applied to GDDR5 product manufactured in 66 nm CMOS process technology and its bandwidth is measured to be greater than 4.0 Gbps on the electric field test.

Cyclic redundancy check (CRC) bits that are conventionally used for error detection have recently found a new application in universal mobile telecommunications system standard for message length detection of variable-length message communications. It was anticipated that the CRC bits, when they are coworked with the inner convolutional code, can be used to detect the receiver-unaware of the message length-without much degradation in their error detection capability. This is unfortunately not true when the offset or difference between the wrong detected length and the true length is small. Two improvements, i.e., the DoCoMo's reverse CRC method and the flip CRC method, were accordingly proposed. In this paper, we revisited the flip CRC modification by considering the impact of joint decoding of the CRC code and the convolutional code. By generalizing the condition for the selection of the flip polynomials, we found that under error-free transmission, the range of the length offsets, at which the false length probability conditioning on the true message length can be made exactly zero (and hence, is minimized), can be extended from to , where and are, respectively, the number of the CRC bits and the memory order of the convolutional code. In addition, an upper bound and a lower bound for the overall false length probability with respect to a uniform pick of the true message length over a candidate message length set are derived. It is then confirmed numerically that the two bounds almost coincide for moderate value. Simulations show that the false length probability obtained analytically under error-free transmission assumption only mildly degrades for moderate-to-high SNRs. Interestingly, we also found that the system block error rate of the flip CRC method can be well approximated by the performance curve of the adopted convolutional code up to a certain SNR, and approach an error floor determined well by the previously derived false length probability bounds beyond this SNR, thereby facilitating the selection of the system parameters, such as the number of CRC bits and the memory order of the convolutional code.

Long BCH codes are broadly used in communications and storage. BCH encoders can be implemented by linear feedback shift registers (LFSRs), and modern systems demand parallel encoders to achieve high speed. LFSRs are also used for implementing cyclic redundancy check (CRC). It was shown previously that adding the input to the least significant tap of the CRC LFSR leads to the lowest complexity in the corresponding parallel architecture derived using state transition. However, the analyses for CRC LFSRs do not hold for long BCH encoders, since the parallelism needed is much smaller than the length of the LFSR for long BCH encoders. Besides, additional clock cycles are required to pad zeros to the input in order to derive the same final state for the parities. This paper first proposes a new parallel design that allows the input to be added to any tap without sacrificing the throughput. Then the matrices involved in parallel long BCH encoders are analyzed to identify the input tap leading to minimum complexity. Besides, hardware unit sharing for matrix multiplications is enabled through analyzing the timing of the encoder. For a 32-parallel (8191, 7684) BCH encoder, our design achieves 57% higher efficiency in terms of throughput/area ratio compared to the best prior design.

Block cyclic redundancy check (CRC) codes represent a popular and powerful class of error detection techniques used almost exclusively in modern data communication systems. Though efficient, CRCs can detect errors only after an entire block of data has been received and processed. In this work, we exploit the nature of error detection that results from using arithmetic codes for error detection, which provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. We demonstrate how this continuous error detection framework improves the overall performance of communication systems, and show how considerable performance gains can be attained. We focus on several important scenarios: 1) automatic repeat request (ARQ) based transmission; 2) forward error correction (FEC frameworks based on (serially) concatenated coding systems involving an inner error-correction code and an outer error-detection code; and 3) reduced state sequence estimation (RSSE) for channels with memory. We demonstrate that the proposed CED framework improves the throughput of ARQ systems by up to 15% and reduces the computational/storage complexity of FEC and RSSE by a factor of two in the comparisons that we make against state-of-the-art systems.

Cyclic Redundancy Check (CRC) is a well-established coding method for error detection and is part of several industrial standards for data transmission and storage. If a second CRC is used on top of an existing standard CRC to provide additional reliability, we call this an embedded CRC. The performance of such CRC combinations has been considered only recently and is not yet well understood. In this paper we propose a sieving method, which can be used to find the best embedded CRC for a given standard CRC, and apply the method to common industry standards for field buses.

Error detection and correction options for data services in B-ISDN (broadband integrated services digital network) are examined. B-ISDN uses the asynchronous transfer mode (ATM) technique for transporting voice, data, and video services. Currently, the ATM cell header size, functions, and adaption layer fields for data services are being standardized in CCITT. Error protection for data payloads will be provided by a per-cell CRC (cyclic redundancy check) field. Different data services may need different degrees of error protection. The authors discuss and analyze different options for error detection and correction by considering various schemes ranging from no error protection to only error detection. Based on the analysis and results presented, a per-cell CRC has been adopted in the adaptation layer for all data services. The per-cell CRC substantially improves cell misdelivery for all data services. For error-insensitive data services, single-bit correction over MID and segment-type fields improves cell loss substantially. At the same time, single-bit correction keeps cell misdelivery sufficiently low (1 in 10/sup 13/ in the worst case). >

This paper investigates the design of optimal vector quantization given channel and error statistics by inclusion of cyclic redundancy checks (CRC) into the consideration. Given a broadcast system with multiresolution vector quantization (MRVQ) and error detection availability for each resolution, a closed-form formula for the weighted end-to-end distortion (EED) is first derived under a random index assignment. Based on the closed-form formula, an iterative algorithm is then proposed for designing optimal MRVQ to minimize the EED with CRC. Experiments show that for a wide range of channel error probability, the inclusion of CRC indeed reduces the EED. Finally, the best tradeoff between the number of bits for quantization and those for CRC is also investigated by experiments.

The rapid growth of the Internet of Things (IoT) and its applications requires high computational efficiency, low-cost, and low-power solutions for various IoT devices. These include a wide range of microcontrollers that are used to collect, process, and transmit IoT data. ESP32 is a microcontroller with built-in wireless connectivity, suitable for various IoT applications. The ESP32 chip is gaining more popularity, both in academia and in the developer community, supported by a number of software libraries and programming languages. While low- and middle-level languages, such as C/C++ and Rust, are believed to be the most efficient, TinyGo and MicroPython are more developer-friendly low-complexity languages, suitable for beginners and allowing more rapid coding. This paper evaluates the efficiency of the available ESP32 programming languages, namely C/C++, MicroPython, Rust, and TinyGo, by comparing their execution performance. Several popular data and signal processing algorithms were implemented in these languages, and their execution times were compared: Fast Fourier Transform (FFT), Cyclic Redundancy Check (CRC), Secure Hash Algorithm (SHA), Infinite Impulse Response (IIR), and Finite Impulse Response (FIR) filters. The results show that the C/C++ implementations were fastest in most cases, closely followed by TinyGo and Rust, while MicroPython programs were many times slower than implementations in other programming languages. Therefore, the C/C++, TinyGo, and Rust languages are more suitable when execution and response time are the key factors, while Python can be used for less strict system requirements, enabling a faster and less complicated development process.

Internet-of-Things (IoT) is growing network paradigm which enables mutual communication between the user and smart devices using the internet. The IoT devices are susceptible to the security threats, due to placement of restricted computational capabilities of the computing devices in IoT. The conventional encryption algorithm utilizes the high amount of resource block in it which increases the area and power. Moreover, Two Factor Authentication (TFA) scheme based authentication protocols does not have the efficiency to secure the data. Because the random number generated by the TFA is ideal for all IoT devices which are easy to hack by the unauthorized persons. In this Research paper, the Linear Feedback Shift Register (LFSR) based Reconfigurable Physical Unclonable Function (RPUF) is proposed to overcome the security issues caused in the IoT communication. The RPUF is designed based on the LFSR to generate the random number for every clock cycle. Normally, reconfigurable process helps to generate the different output values for every clock cycle. But, it failed to generate different outputs for same input values. Here, LFSR based RPUF helps to generated the different response values even the same challenge is given to the input side. The Lightweight TFA scheme is presented for IoT, where PUF has been considered as one of the major authentication factors. At last, Spartan 6 and Virtex 6 Field Programmable Gate Array (FPGA) performances are calculated for proposed TFA-RPUF-IoT and existing TFA-PUF-IoT protocols. In Spartan 6, TFA-RPUF-IoT protocol occupied 11 slices, 31 LUTs, 42 flip flops which are less compared to conventional TFA-PUF-IoT.

Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Although efficient, CRCs can detect errors only after an entire block of data has been received and processed. We propose a new continuous error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection, first introduced by Bell, Witten, and Cleary (1990), is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error.