Continuous object access profiling and optimizations to overcome the memory wall and bloat

As the computing environments are continuously moving towards battery-operated mobile and handheld systems, the development of energy-saving mechanisms for such devices has recently become a technical challenge. Dynamic voltage scaling (DVS) has historically been considered an effective method to reduce the processor power consumption. Conventional DVS techniques typically consider only processor utilisation issues in a policy-making process. However, as memory-bound multimedia applications are becoming popular in handheld devices, the DVS policies should consider the so-called ‘memory wall’ problem to maximise energy gain. Recent DVS techniques suffer from the inefficiency of their policies caused by the memory-wall problem while executing multimedia applications, and no previous research on DVS considers the problem explicitly. The existence of the memory wall problem in a real system is revealed and a metric that can be used to detect the problem in advance is found. A memory-aware DVS (M-DVS) technique that takes the memory wall problem fully into consideration is proposed. The experimental results on a PDA show that M-DVS can reduce ∼8% of additional power consumption, compared with conventional DVS, without any QoS degradation for handling multimedia clips.

The advent of manycore in computing architecture causes severe energy consumption and memory wall problem. Thus, emerging technologies such as on-chip memory and nonvolatile memory (NVRAM) have led to a paradigm shift in computing architecture era. For instance, nonvolatile memories like PRAM can be viable DRAM replacements, achieving competitive speeds at lower power consumption. On-chip memory such as 3D-stacked memory can solve the limitation of memory bandwidth. The confluence of these trends offers a new opportunity to rethink traditional computing system and memory hierarchies.In an attempt to mitigate the energy and memory wall, we propose a new architecture with a hierarchical and a hybrid main memory for manycore system, termed MN-MATE. The hierarchical memory consists of on-chip memory, which is called M1 memory, and a conventional DRAM memory is replaced by a hybrid memory of DRAM and PRAM, called M2 memory. On the top of the system, we designed and evaluated efficient management techniques to achieve the high performance and the low energy usage, including hierarchical memory management, power-aware hybrid memory management, and file caching on a hybrid memory. Preliminary results show that these techniques can improve performance and reduce energy usage. As a case study, we introduce the MaaS (Matching-as-a-Service) application which requires the large amount of memory and high computing power.

Sparse matrix-vector multiplication (SpMV) is a challenging computational kernel in linear algebra applications, like data mining, image processing, and machine learning. The performance of this kernel is greatly dependent on the size of the input matrix and the underlying hardware features. Various sparse matrix storage formats referred to commonly as sparse formats have been proposed in the literature to reduce the size of the matrix. In modern multi-core and many-core architectures, the performance of the kernel is mainly dependent on memory wall and power wall problem. Normally review on sparse formats is done with specific architecture or with specific application. This chapter presents a comparative study on various sparse formats in cross platform architecture like CPU, graphics processor unit (GPU), and single instruction multiple data stream (SIMD) registers. Space complexity analysis of various formats with its representation is discussed. Finally, the merits and demerits of each format have been summarized into a table.

Derivative information plays a crucial role in the correctness and performance of scientific computing in a wide variety of scientific domains such as computational fluid dynamics (CFD), finance engineering and so on. The reverse mode of Algorithmic Differentiation is particularly efficient for the computation of derivatives of multivariate vector functions <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$F: R^{n}\mapsto R^{m}$</tex> , where the number of inputs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n$</tex> far exceeds the number of outputs <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$m$</tex> , frequently appearing as cost functions in numerical optimization kernels. In particular, reverse-mode AD is at the heart of the back propagation algorithm widely used in machine learning. The reverse mode of AD requires that the control flow of the derivative program be reversed, meaning that the results of intermediate computations (in our case, the computational graph of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$F$</tex> ) must be stored either in memory or secondary storage. As a result, this requirement leads to the memory wall problem, especially for large-scale numerical problems, where the results of intermediate computations cannot fit entirely in memory. In this paper, we present an algorithm called Memory-Efficient Adjoints (ME-Adjoints) for solving the memory wall problem by dynamically applying a simple partitioning scheme to the computational graph of the function <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$F$</tex> at runtime. Our approach employs operator overloading in C++ to achieve a fully automatic adjoining process, whereby derivative programs require only trivial changes to the code as opposed to the use of checkpointing techniques, which require substantial changes to the code.

As CPU frequency and computing power grow fast, conventional Von Neumann architecture is suffering from more and more severe data transfer latency and power consumption between CPU and DRAM, known as memory wall problem. In this paper, we propose a novel near memory architecture based on the H-tree architecture of DRAM to decrease the data transfer latency. There are three work modes in the proposed CoDRAM, GMM (General Main Memory Mode), ACM (Auxiliary Computing Mode) and PCM (Parallel Computing Mode). Compared with conventional CPU+DRAM architecture, the experiment shows that the proposed CoDRAM computing framework can improve about 20% and 33% performance on matrix addition and integral image computing in ACM mode. And in PCM mode, the improvement is about 15× and 3× in matrix addition and integral image computing. Meanwhile, the overhead in GMM mode is only about 1%.

The memory wall problem is one of the important issues in modern computer system - it affects the system performance in spite of the powerful processor. The emergence of multi-core processors has further exacerbated the problem. On the other hand, the increasing use of the linked data structure in applications aggravates the memory access latency. This paper dispatches two thread prefetching techniques based on CMP which prefetches the demanded data into the shared cache in advance to hide the long memory access latency, and evaluates these two helper thread prefetching algorithms based on three fundamental aspects of data prefetching. The performance evaluation of thread prefetching shows with acceptable coverage, increasing timeliness and accuracy can improve performance of threaded prefetching. However, improving accuracy by issuing prefetches earlier introduces more uncertainty in the prefetching, hence reducing coverage. Performance results of four benchmark applications when applying with two thread prefetching techniques is also provided.

Before the advent of modern supercomputers, single processors were approaching the limit of improvement in operating frequency, and there was a memory wall problem. Even if the computing capacity of a single processor could be increased, the data supply capacity of the memory could not match the computing capacity. The increase in operating frequency also caused the problem, that is, power consumption increased faster than performance improvement. In other words, the limit of performance improvement of a single processor was becoming apparent. To solve these problems, parallel architectures, in which many single processors are connected by a communication mechanism, have been used. The two points, “programming conscious of parallelism” and “programming conscious of execution performance”, are very important for users, researchers, and programmers to make effective use of the present supercomputers equipped with tens of thousands of processors.

Asynchronous memory operations provide a means for coping with the memory wall problem in multicore processors, and are available in many platforms and languages, e.g., the Cell Broadband Engine, CUDA and OpenCL. Reasoning about the correct usage of such operations involves complex analysis of memory accesses to check for races. We present a method and tool for proving memory-safety and race-freedom of multicore programs that use asynchronous memory operations. Our approach uses separation logic with permissions, and our tool automates this method, targeting a C-like core language. We describe our solutions to several challenges that arose in the course of this research. These include: syntactic reasoning about permissions and arrays, integration of numerical abstract domains, and utilization of an SMT solver. We demonstrate the feasibility of our approach experimentally by checking absence of DMA races on a set of programs drawn from the IBM Cell SDK.

Most of the microprocessor spends majority of its time waiting for the data to be transferred from slow memory devices connected to it, resulting in Memory wall problem. The main aim of this paper is to reduce memory wall problem by increasing not only processor speed but also the memory speed. This can be achieved by placing efficient and small memory near the processor so that energy efficiency of the system can be improved. Such memory is called Scratch Pad memory (SPM). Scratch pad memory (SPM) and cache memory plays a vital role in improving the efficiency of the system. Repositioning of code in on-chip and off-chip memory increases the efficient of the utilization of multiprocessing embedded system. Optimal code layout design is developed to place the code in memory for preventing the cache conflicts and misses. Many researchers discussed about the usage of SPM and cache memory to improve the efficiency of the system but combining the both is not done. In this work both SPM and cache memory is combined with the proposed Meta heuristics technique. Meta heuristic model is the proposed model in which along with the SPM, Cache code layout is developed to place the code in it, resulting better performance compared with the other two models namely ILP model and Heuristic model. It is found that the two stage meta-heuristic model yield more efficiency and consume less energy than other two models.

The cost of accessing main memory is increasing. Machine designers have tried to mitigate the consequences of the processor and memory technology trends underlying this increasing gap with a variety of techniques to reduce or tolerate memory latency. These techniques, unfortunately, are only occasionally successful for pointer-manipulating programs. Recent research has demonstrated the value of a complementary approach, in which pointer-based data structures are reorganized to improve cache locality.This paper studies a technique for using a generational garbage collector to reorganize data structures to produce a cache-conscious data layout, in which objects with high temporal affinity are placed next to each other, so that they are likely to reside in the same cache block. The paper explains how to collect, with low overhead, real-time profiling information about data access patterns in object-oriented languages, and describes a new copying algorithm that utilizes this information to produce a cache-conscious object layout.Preliminary results show that this technique reduces cache miss rates by 21--42%, and improves program performance by 14--37% over Cheney's algorithm. We also compare our layouts against those produced by the Wilson-Lam-Moher algorithm, which attempts to improve program locality at the page level. Our cache-conscious object layouts reduces cache miss rates by 20--41% and improves program performance by 18--31% over their algorithm, indicating that improving locality at the page level is not necessarily beneficial at the cache level.

Scala is a new programming language bringing together object-oriented and functional programming. Its defining features are uniformity and extensibility. Scala offers great flexibility for programmers, allowing them to grow the language through libraries. Oftentimes what seems like a language feature is in fact implemented in a library, effectively giving programmers the power of language designers. The downside of this flexibility is that familiar looking code may hide unexpected performance costs. It is important for Scala compilers to bring down this cost as much as possible. We identify several areas of impact for Scala performance: higher-order functions and closures, and generic containers used with primitive types. We present two complementary approaches for improving performance in these areas: optimizations and specialization. Compiler optimization can bring down the cost through a combination of aggressive inlining of higher-order functions, an extended version of copy-propagation and dead-code elimination. Both anonymous functions and boxing can be eliminated by this approach. We show on a number of benchmarks that these language features can be up to 5 times faster when properly optimized, on current day JVMs. We propose a new approach to compiling parametric polymorphism for performance at primitive types. We mix a homogeneous translation scheme with user-directed specialization for primitive types. Type parameters may be annotated to require specialization of code depending on them. We propose definition-site specialization for primitive types, achieving separate compilation and no boxing when both the definition and call site are specialized. Specialized classes are compatible with unspecialized code, and specialization agnostic code can work with specialized instances, meaning that specialization is opportunistic. We present a formalism of a small subset of Scala with specialization and prove that specialization preserves types. We implemented this translation in the Scala compiler and report on improvements on a set of benchmarks, showing that specialization can make programs more than two times faster.

Domain-expert productivity programmers desire scalable application performance, but usually must rely on efficiency programmers who are experts in explicit parallel programming to achieve it. Since such programmers are rare, to maximize reuse of their work we propose encapsulating their strategies in mini-compilers for domain-specific embedded languages (DSELs) glued together by a common high-level host language familiar to productivity programmers. The nontrivial applications that use these DSELs perform up to 98% of peak attainable performance, and comparable to or better than existing hand-coded implementations. Our approach is unique in that each mini-compiler not only performs conventional compiler transformations and optimizations, but includes imperative procedural code that captures an efficiency expert's strategy for mapping a narrow domain onto a specific type of hardware. The result is source- and performance-portability for productivity programmers and parallel performance that rivals that of hand-coded efficiency-language implementations of the same applications. We describe a framework that supports our methodology and five implemented DSELs supporting common computation kernels.Our results demonstrate that for several interesting classes of problems, efficiency-level parallel performance can be achieved by packaging efficiency programmers' expertise in a reusable framework that is easy to use for both productivity programmers and efficiency programmers.

4678762 Very smooth and flat polycrystalline alumina substrates from direct firing

Studies for more than two decades have uncovered a variety of difficulties and misconceptions that novice programmers have with object-oriented programming (OOP). Particularly challenging are the threshold concepts of program dynamics. Studies show that engaging learning approaches may be helpful. One such approach is that of capitalizing on errors, which has been successfully applied in mathematics and physics education. The learning-from-errors approach embedded in an OOP course may improve novices’ comprehension of OOP program dynamics notions and promote the embedment of such an approach in teaching. An instructional approach capitalizing on cognitive conflicts and conflict resolution was designed, applied, and evaluated. The approach involved declarative specifications of the fundamental, challenging notions of object creation and object access. The specifications embodied the mental models at which the instruction was aimed. Focused learning-from-errors activities based on minimalism principles were developed and applied. A comparative evaluation of an experimental group and a control group showed that the experimental-group students were more successful, particularly with the assimilation of the notions of object creation, object identifiers, static elements, and encapsulation. The learning-from-errors approach may be applied in additional domains, including other programming paradigms.

Byte-addressable non-volatile memory is poised to become prevalent in the near future. Thanks to device-level technological advances, hybrid systems of traditional dynamic random-access memory (DRAM) coupled with non-volatile random-access memory (NVRAM) are already present and are expected to be commonplace soon. NVRAM offers orders of magnitude performance improvements over existing storage devices. Due to NVRAM's low overheads, many future applications are expected to leverage the fine-grain durable storage provided by NVRAM.