Controlled gates for multi-level quantum computation

Multiple-valued reversible logic is an emerging area in reversible and quantum logic circuit synthesis. Multiple-valued reversible logic circuits can potentially reduce the width of the reversible or quantum circuit which is a limitation in current quantum technology. In this paper we propose a method to synthesize the multiple-valued reversible sequential circuits. Implementations for ternary D and T flip flops and edge triggered D flip flop are proposed. Synthesis of generalized fanout circuit and generalized r-valued T flip flop are also presented.

Quantum computation can solve certain problems much faster than classical computation. However, quantum computations are more susceptible to errors than conventional digital computations. Thus, a fault-tolerant (FT) quantum circuit design is required for a practical implementation. Quantum circuits consist of a cascade of quantum gates. These gates are themselves realized using primitive quantum operations that are supported by the quantum physical machine description (PMD). As different quantum systems are associated with different Hamiltonians, they have different PMDs. In addition, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for the set of primitive quantum operations supported by the given PMD. In this paper, an FT quantum logic synthesis (FTQLS) methodology and tool is described for six different PMDs. A methodology, such as this, which can be targeted at multiple PMDs, has not been attempted before, to the best of our knowledge. The input to FTQLS is an unoptimized quantum circuit realized using a set of commonly used gates and its output is an optimized FT quantum circuit that only comprises of primitive quantum operations supported by the given PMD. FTQLS does technology mapping for different PMDs and then converts non-FT circuits to FT circuits. For technology mapping, it utilizes an optimized quantum gate library targeted at various PMDs that decomposes gates into primitive operations. Efficient conversion to FT circuits is done by integrating two quantum compilers and an FT cache table into FTQLS. For improving the synthesis results, an FT set of gates that is directly supported by each PMD is proposed. Quantum circuit optimization is done by utilizing quantum identity rules. The performance of FTQLS is evaluated using two cost metrics: number of primitive operations (#ops) and execution cycles on the critical path (#cycles). Experiment results show that the decrease in #ops varies between 58.1% and 87.0% and in #cycles between 42.8% and 76.4%, on an average, depending on the PMD.

Detection and isolation of faults is a crucial step in the physical realization of quantum circuits. Even though quantum gates and circuits compute reversible functions, the standard techniques of automatic test pattern generation (ATPG) for classical reversible circuits are not directly applicable to quantum circuits. For faulty quantum circuits under the widely accepted single fault assumption, we show that their behavior can be fully characterized by the (single) faulty gate and the corresponding fault model. This allows us to efficiently determine test input states as well as measurement strategy for fault detection and diagnosis. Building on top of these, we design randomized algorithms which are able to detect every nontrivial single-gate fault with minimal probability of error. We also describe similar algorithms for fault diagnosis. We evaluate our algorithms by the number of output samples that needs to be collected and the probability of error. Both of these can be related to the eigenvalues of the operators corresponding to the circuit gates. We experimentally compare all our strategies with the state-of-the-art ATPG techniques for quantum circuits under the “single missing faulty gate” model and demonstrate that significant improvement is possible if we can exploit the quantum nature of circuits.

In order to improve the training efficiency of the support vector machine, a quantum circuit training scheme based on the inner product of the quantum state for the support vector machine is proposed in this work. Firstly, on the basis of the full analysis of the computational complexity of the classical support vector machine, the kernel function which is the main factor affecting the computational complexity of the algorithm is primarily analyzed. Based on quantum mechanics and quantum computing theory, the training sample elements in the kernel function are quantized to generate the corresponding quantum states. Secondly, according to the quantum states of the training sample elements, the types and quantities of the required quantum logic gates are derived and calculated, and the quantum circuit that can generate the corresponding quantum states of the training sample elements through the evolution of the quantum initial ground states and the quantum logic gates is designed. Then, in the light of the relationship between the inner product of the quantum state and the quantum logic gate SWAP, the quantum circuit is designed to complete the exchange operation of the corresponding quantum state amplitude. The inner product of the quantum state is realized by exchanging and evolving the amplitude of the quantum state in the quantum circuit. Finally, by measuring the quantum state of the controlling qubit, the inner product solution of the kernel function is obtained, and the acceleration effect of training support vector machine is realized. The verification results show that the scheme enables the support vector machine not only to complete the correct classification, but also to operate the quantum part of the scheme on the real quantum computer . Compared with the classical algorithm, the scheme reduces the time complexity of the algorithm for the polynomial degree, greatly shortens the training time of the model, and improves the efficiency of the algorithm. The scheme has certain feasibility, effectiveness and innovation, and expands the training idea of the support vector machine.

The semiconductor industry has been experiencing a massive upgradation in terms of speed and device performance due to device scaling since the invention of MOSFETs in 1960s, but simultaneously power dissipation has also been a major concern. With the device scaling having reached its limit, researchers are looking for a breakthrough technology. One of the emerging fields in the VLSI industry is Reversible Computing. This technology has largely attracted the researchers, because of zero power dissipation in reversible logic circuits. The proposed work here is towards designing an ALU using reversible quantum gates, which operate on qubits. The proposed ALU performs both arithmetic and logical operations, either of which can be selected as per the requirement and additionally, it is capable of detecting single bit error. The design uses Fredkin and CNOT gate, which are parity preserving reversible gates. The proposed design is modelled using Verilog HDL and simulated in Modelsim software. The design is focused on reducing the number of gates, quantum cost, Garbage outputs and ancillary inputs or constant inputs.

ABSTRACTQuantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.

The Quantum Multiple-valued Decision Diagram (QMDD) data-structure has been introduced as a means for an efficient representation and manipulation of transformation matrices realized by quantum or reversible logic circuits. A particular challenge is the handling of arbitrary complex numbers as they frequently occur in quantum functionality. These numbers are represented through edge weights which, however, represent a severe obstacle with respect to canonicity, modifiability, and applicability of QMDDs. Previously introduced approaches did not provide a satisfactory solution to these obstacles. In this paper, we propose an improved factorization scheme for complex numbers that ensures a canonical representation while, at the same time, allows for local changes. We demonstrate how the proposed solution can be exploited to improve the data-structure itself (e.g. through variable re-ordering enabled by the advanced modifiability) and how applications such as equivalence checking benefit from that.

The construction of quantum computers is based on the synthesis of low-cost quantum circuits. The quantum circuit of any Boolean function expressed in a Positive Polarity Reed-Muller (PPRM) expansion can be synthesized using Multiple-Control Toffoli (MCT) gates. This paper proposes two algorithms to construct a quantum circuit for any Boolean function expressed in a PPRM expansion. The Boolean function can be expressed with various algebraic forms, so there are different quantum circuits can be synthesized for the Boolean function based on its algebraic form. The proposed algorithms aim to map the MCT gates into the NCV gates for any quantum circuit by generating a simple algebraic form for the Boolean function. The first algorithm generates a special algebraic form for any Boolean function by rearrangement of terms of the Boolean function according to a predefined degree of term d term , then synthesizes the corresponding quantum circuit. The second algorithm applies the decomposition methods to decompose MCT circuit into its elementary gates followed by applying a set of simplification rules to simplify and optimize the synthesized quantum circuit. The proposed algorithms achieve a reduction in the quantum cost of synthesized quantum circuits when compared with relevant work in the literature. The proposed algorithms synthesize quantum circuits that can applied on IBM quantum computer.

The theory of logical gates in quantum computation has inspired the development of new forms of quantum logic where the meaning of a formula is identified with a density operator and the logical connectives are interpreted as operations defined in terms of quantum gates. We show some relations between the Bertini gate and many valued connectives by probability values. On this basis, one can deal with quantum circuits as expressions in an algebraic environment such as product many valued algebra for combinational circuits. As can be expected, we show that the compositional logic characterized by the qubit semantics is stronger than the compositional Łukasiewicz quantum computational logic by a counterexample. But, in the holistic case, we conjecture that they can characterize the same logic.

Delay is an important parameter that needs to be considered in the reversible logic designs, but not much work on delay in reversible network has been done at present. This paper presents an algorithm to calculate delay of reversible network. In the process of calculating delay, we not only take the complexity of different logic gates into consideration, but also the relationship between the output delay of the target bits and all inputs delay of the controlled reversible logic gates is considered. We use the algorithm to calculate the delay in reversible logic circuits synthesized and optimized by several different reversible logic synthesis methods. Then we analyze the performance of these reversible logic synthesis methods in delay level. Through the comparative analysis, we prove that these reversible logic synthesis methods for some function in reducing quantum cost have a good effect, but not in delay level. The quantum cost of some reversible logic circuits which have the same function is less, however the delay may not.

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

Non-adiabatic holonomic quantum gate in decoherence-free subspaces is of greatly practical importance due to its built-in fault tolerance, coherence stabilization virtues, and short run-time. Here, we propose some compact schemes to implement two- and three-qubit controlled unitary quantum gates and Fredkin gate. For the controlled unitary quantum gates, the unitary operator acting on the target qubit is an arbitrary single-qubit gate operation. The controlled quantum gates can be directly implemented by utilizing non-adiabatic holonomy in decoherence-free subspaces and the required resource for the decoherence-free subspace encoding is minimal by using only two neighboring physical qubits undergoing collective dephasing to encode a logical qubit.

We propose an approach to optimally synthesize quantum circuits from\nnon-permutative quantum gates such as Controlled-Square-Root-of-Not (i.e.\nControlled-V). Our approach reduces the synthesis problem to multiple-valued\noptimization and uses group theory. We devise a novel technique that transforms\nthe quantum logic synthesis problem from a multi-valued constrained\noptimization problem to a group permutation problem. The transformation enables\nus to utilize group theory to exploit the properties of the synthesis problem.\nAssuming a cost of one for each two-qubit gate, we found all reversible\ncircuits with quantum costs of 4, 5, 6, etc, and give another algorithm to\nrealize these reversible circuits with quantum gates.\n

Quantum Gates and Quantum Circuits of Stock Portfolio

We present a quantum computing algorithm for fluid flows based on the Carleman-linearization of the Lattice Boltzmann (LB) method. First, we demonstrate the convergence of the classical Carleman procedure at moderate Reynolds numbers, namely, for Kolmogorov-like flows. Then we proceed to formulate the corresponding quantum algorithm, including the quantum circuit layout, and analyze its computational viability. We show that, at least for moderate Reynolds numbers between 10 and 100, the Carleman–LB procedure can be successfully truncated at second order, which is a very encouraging result. We also show that the quantum circuit implementing the single time-step collision operator has a fixed depth, regardless of the number of lattice sites. However, such depth is of the order of ten thousands quantum gates, meaning that quantum advantage over classical computing is not attainable today, but could be achieved in the near or mid-term future. The same goal for the multi-step version remains, however, an open topic for future research.